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e365338a88
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Update Quartus project files
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2023-03-30 16:42:29 +02:00 |
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6ee3e16559
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Implement a CPU TestBench
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2023-03-30 16:29:07 +02:00 |
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12f9412b55
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Fix some timing bugs in the CPU and add debug outputs
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2023-03-30 16:28:53 +02:00 |
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0224bdc664
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Make Program in ROM start at address 1
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2023-03-30 16:28:15 +02:00 |
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dc4f25dc89
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Remove the clock inputs from ALU and Cond again (for now)
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2023-03-30 16:27:56 +02:00 |
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547472098f
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More compact wire definitions in CPU
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2023-03-30 13:31:02 +02:00 |
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ff0ab6c28f
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Update Quartus project files
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2023-03-30 13:27:59 +02:00 |
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5b0d12183d
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Remove unnecessary default case from ConditionalUnit
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2023-03-30 13:22:45 +02:00 |
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fb2667affa
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Add empty CPU TestBench
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2023-03-30 13:20:24 +02:00 |
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439480b124
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Remove implicit latches from the CPU bus
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2023-03-30 13:19:36 +02:00 |
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c59eec85d1
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Add arg outputs to Controller
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2023-03-30 13:19:12 +02:00 |
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139674163b
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Widthcast increment/decrement in Counter
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2023-03-30 13:19:00 +02:00 |
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5d8757737f
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Update Quartus project files
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2023-03-30 00:22:01 +02:00 |
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db3f906d2b
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Implement CPU Controller
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2023-03-30 00:21:56 +02:00 |
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f472994fda
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Add clock input to ALU/ConditionalUnit
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2023-03-30 00:21:47 +02:00 |
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dc83546ed2
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Add permanent reg0 output to RegisterFile
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2023-03-30 00:21:31 +02:00 |
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72f7f6ca18
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Parametrize the counter bit width
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2023-03-30 00:21:15 +02:00 |
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88a72358f7
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Implement CPU "cycle" decoder
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2023-03-30 00:21:01 +02:00 |
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c2f92ccb66
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Implement an example program using ROM
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2023-03-29 19:28:32 +02:00 |
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0f7f2742fd
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Implement Counter TestBench
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2023-03-29 17:08:24 +02:00 |
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788cf7566b
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Reformat Counter
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2023-03-29 16:04:13 +02:00 |
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0ba622d9c0
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Update Quartus project files
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2023-03-29 15:59:23 +02:00 |
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6366984b50
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Implement RegisterFile TestBench
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2023-03-29 15:59:09 +02:00 |
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ea5b2c53c2
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Add missing "signed" to ALU ports/connections
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2023-03-29 15:03:20 +02:00 |
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17493586ff
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Implement ALU TestBench
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2023-03-29 14:31:50 +02:00 |
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d57673d5a4
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Fix the ALU sensitivity list
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2023-03-29 14:31:45 +02:00 |
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c07c736de9
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Small renaming
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2023-03-29 14:31:35 +02:00 |
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5128478af7
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Implement TestBench for ArithmeticUnit
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2023-03-29 13:57:23 +02:00 |
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c477148480
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Implement TestBench for LogicalUnit
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2023-03-29 13:57:15 +02:00 |
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57b6316769
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Fix sensitivity list of LogicalUnit
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2023-03-29 13:54:56 +02:00 |
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3d8270b89b
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Fix sensitivity list for AithmeticUnit
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2023-03-29 13:54:44 +02:00 |
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f21d4676c4
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Add Quartus project files
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2023-03-27 23:30:38 +02:00 |
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6c9a027209
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Add .gitignore
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2023-03-27 23:29:39 +02:00 |
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49d1871dfa
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Implement ALU/Register components
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2023-03-23 21:51:50 +01:00 |
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