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• e365338a88 Update Quartus project files main christoph 2023-03-30 16:42:29 +02:00
• 6ee3e16559 Implement a CPU TestBench christoph 2023-03-30 16:29:07 +02:00
• 12f9412b55 Fix some timing bugs in the CPU and add debug outputs christoph 2023-03-30 16:28:53 +02:00
• 0224bdc664 Make Program in ROM start at address 1 christoph 2023-03-30 16:28:15 +02:00
• dc4f25dc89 Remove the clock inputs from ALU and Cond again (for now) christoph 2023-03-30 16:27:56 +02:00
• 547472098f More compact wire definitions in CPU christoph 2023-03-30 13:31:02 +02:00
• ff0ab6c28f Update Quartus project files christoph 2023-03-30 13:27:59 +02:00
• 5b0d12183d Remove unnecessary default case from ConditionalUnit christoph 2023-03-30 13:22:45 +02:00
• fb2667affa Add empty CPU TestBench christoph 2023-03-30 13:20:24 +02:00
• 439480b124 Remove implicit latches from the CPU bus christoph 2023-03-30 13:19:36 +02:00
• c59eec85d1 Add arg outputs to Controller christoph 2023-03-30 13:19:12 +02:00
• 139674163b Widthcast increment/decrement in Counter christoph 2023-03-30 13:19:00 +02:00
• 5d8757737f Update Quartus project files christoph 2023-03-30 00:22:01 +02:00
• db3f906d2b Implement CPU Controller christoph 2023-03-30 00:21:56 +02:00
• f472994fda Add clock input to ALU/ConditionalUnit christoph 2023-03-30 00:21:47 +02:00
• dc83546ed2 Add permanent reg0 output to RegisterFile christoph 2023-03-30 00:21:31 +02:00
• 72f7f6ca18 Parametrize the counter bit width christoph 2023-03-30 00:21:15 +02:00
• 88a72358f7 Implement CPU "cycle" decoder christoph 2023-03-30 00:21:01 +02:00
• c2f92ccb66 Implement an example program using ROM christoph 2023-03-29 19:28:32 +02:00
• 0f7f2742fd Implement Counter TestBench christoph 2023-03-29 17:08:24 +02:00
• 788cf7566b Reformat Counter christoph 2023-03-29 16:04:13 +02:00
• 0ba622d9c0 Update Quartus project files christoph 2023-03-29 15:59:23 +02:00
• 6366984b50 Implement RegisterFile TestBench christoph 2023-03-29 15:59:09 +02:00
• ea5b2c53c2 Add missing "signed" to ALU ports/connections christoph 2023-03-29 15:03:20 +02:00
• 17493586ff Implement ALU TestBench christoph 2023-03-29 14:31:50 +02:00
• d57673d5a4 Fix the ALU sensitivity list christoph 2023-03-29 14:31:45 +02:00
• c07c736de9 Small renaming christoph 2023-03-29 14:31:35 +02:00
• 5128478af7 Implement TestBench for ArithmeticUnit christoph 2023-03-29 13:57:23 +02:00
• c477148480 Implement TestBench for LogicalUnit christoph 2023-03-29 13:57:15 +02:00
• 57b6316769 Fix sensitivity list of LogicalUnit christoph 2023-03-29 13:54:56 +02:00
• 3d8270b89b Fix sensitivity list for AithmeticUnit christoph 2023-03-29 13:54:44 +02:00
• f21d4676c4 Add Quartus project files christoph 2023-03-27 23:30:38 +02:00
• 6c9a027209 Add .gitignore christoph 2023-03-27 23:29:39 +02:00
• 49d1871dfa Implement ALU/Register components christoph 2023-03-23 21:51:50 +01:00