christoph/quartus-8-bit-cpu
1
Fork 0
Code Activity

Update Quartus project files

Browse Source
This commit is contained in:
Christoph Urlacher
2023-03-30 00:22:01 +02:00
parent db3f906d2b
commit 5d8757737f
2 changed files with 123 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
CPU.qsf
View File

@ -39,7 +39,7 @@
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CGXFC5C6F27C7
set_global_assignment -name TOP_LEVEL_ENTITY Counter_TestBench
set_global_assignment -name TOP_LEVEL_ENTITY Decoder_TestBench
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:27:08 MäRZ 23, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
@ -66,7 +66,7 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH Counter_TestBench -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH Decoder_TestBench -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME ALU_TestBench -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ALU_TestBench
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ALU_TestBench -section_id ALU_TestBench
@ -93,15 +93,24 @@ set_global_assignment -name EDA_TEST_BENCH_NAME RegisterFile_TestBench -section_
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id RegisterFile_TestBench
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME RegisterFile_TestBench -section_id RegisterFile_TestBench
set_global_assignment -name SYSTEMVERILOG_FILE Counter_TestBench.sv
set_global_assignment -name EDA_TEST_BENCH_NAME Counter_TestBench -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id Counter_TestBench
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME Counter_TestBench -section_id Counter_TestBench
set_global_assignment -name SYSTEMVERILOG_FILE ROM.sv
set_global_assignment -name SYSTEMVERILOG_FILE CPU.sv
set_global_assignment -name SYSTEMVERILOG_FILE Controller.sv
set_global_assignment -name EDA_TEST_BENCH_FILE ALU_TestBench.sv -section_id ALU_TestBench
set_global_assignment -name EDA_TEST_BENCH_FILE LogicalUnit_TestBench.sv -section_id LogicalUnit_TestBench
set_global_assignment -name EDA_TEST_BENCH_FILE ArithmeticUnit_TestBench.sv -section_id ArithmeticUnit_TestBench
set_global_assignment -name EDA_TEST_BENCH_FILE ConditionalUnit_TestBench.sv -section_id ConditionalUnit_TestBench
set_global_assignment -name EDA_TEST_BENCH_FILE RegisterFile_TestBench.sv -section_id RegisterFile_TestBench
set_global_assignment -name EDA_TEST_BENCH_NAME Counter_TestBench -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id Counter_TestBench
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME Counter_TestBench -section_id Counter_TestBench
set_global_assignment -name EDA_TEST_BENCH_FILE Counter_TestBench.sv -section_id Counter_TestBench
set_global_assignment -name EDA_TEST_BENCH_NAME Decoder_TestBench -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id Decoder_TestBench
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME Decoder_TestBench -section_id Decoder_TestBench
set_global_assignment -name EDA_TEST_BENCH_FILE Decoder.sv -section_id Decoder_TestBench
set_global_assignment -name SYSTEMVERILOG_FILE Decoder.sv
set_global_assignment -name SYSTEMVERILOG_FILE Decoder_TestBench.sv
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top

109
CPU.sv Normal file
View File

@ -0,0 +1,109 @@
`default_nettype none
module CPU(
input var logic enable,
input var logic clock,
input var logic reset
);
// Decoder
var logic fetch, decode, execute, writeback;
var logic clk;
assign clk = enable && clock; // Only clock the CPU when enabled
Decoder dec(
.clock(clk),
.reset(reset),
.fetch(fetch),
.decode(decode),
.execute(execute),
.writeback(writeback)
);
// Program Counter
var logic pc_set;
var logic[7:0] pc_in;
var logic[7:0] pc_out;
Counter pc(
.clock(fetch), // WARNING: Phase 1 - Fetch
.reset(reset),
.decrement(0),
.setvalue(pc_set),
.valuein(pc_in),
.valueout(pc_out)
);
// ROM (Instruction Memory)
var logic[7:0] rom_data;
ROM rom(
.address(pc_out),
.dataout(rom_data)
);
// Controller
var logic[1:0] ctrl_opcode;
var logic ctrl_regsset, ctrl_pcset;
var logic[2:0] ctrl_regssavesel, ctrl_regsloadsel, ctrl_aluopc, ctrl_condopc;
Controller ctrl(
.clock(decode), // WARNING: Phase 2 - Decode
.reset(reset),
.databus(rom_data),
.opcode(ctrl_opcode),
.regs_set(ctrl_regsset),
.regs_savesel(ctrl_regssavesel),
.regs_loadsel(ctrl_regsloadsel),
.alu_opc(ctrl_aluopc),
.cond_opc(ctrl_condopc),
.pc_set(ctrl_pcset)
);
// Register Bank
var logic[7:0] regs_savebus;
var logic[7:0] regs_loadbus;
var logic[7:0] regs_jumptarget;
var logic[7:0] regs_aluopA;
var logic[7:0] regs_aluopB;
var logic[7:0] regs_aluresult;
RegisterFile regs(
.clock(writeback), // WARNING: Phase 4 - Writeback
.reset(reset),
.save(ctrl_regsset),
.saveselector(ctrl_regssavesel),
.savebus(regs_savebus),
.loadselector(ctrl_regsloadsel),
.loadbus(regs_loadbus),
.jumptarget(regs_jumptarget),
.aluoperandA(regs_aluopA),
.aluoperandB(regs_aluopB),
.aluresult(regs_aluresult)
);
// Arithmetic and Logical Unit
var logic[7:0] alu_result;
ALU alu(
.clock(execute), // WARNING: Phase 3 - Execute
.opcode(ctrl_aluopc),
.operandA(regs_aluopA),
.operandB(regs_aluopB),
.result(alu_result)
);
// Conditional Unit
var logic cond_result;
ConditionalUnit cond(
.clock(execute), // WARNING: Phase 3 - Execute
.opcode(ctrl_condopc),
.operand(regs_aluresult),
.result(cond_result)
);
// CPU Inter-Component Connections
assign pc_set = cond_result && ctrl_pcset;
assign pc_in = regs_jumptarget;
always @(execute) case (ctrl_opcode)
2'b01: regs_savebus = alu_result;
2'b11: regs_savebus = regs_loadbus;
default: regs_savebus = 8'b00000000;
endcase
endmodule