ChUrl 547472098f More compact wire definitions in CPU

2023-03-30 13:31:02 +02:00

.gitignore

Add .gitignore

2023-03-27 23:29:39 +02:00

ALU_TestBench.sv

Add missing "signed" to ALU ports/connections

2023-03-29 15:03:20 +02:00

ALU.sv

Add clock input to ALU/ConditionalUnit

2023-03-30 00:21:47 +02:00

ArithmeticUnit_TestBench.sv

Add missing "signed" to ALU ports/connections

2023-03-29 15:03:20 +02:00

ArithmeticUnit.sv

Add missing "signed" to ALU ports/connections

2023-03-29 15:03:20 +02:00

ConditionalUnit_TestBench.sv

Add missing "signed" to ALU ports/connections

2023-03-29 15:03:20 +02:00

ConditionalUnit.sv

Remove unnecessary default case from ConditionalUnit

2023-03-30 13:22:45 +02:00

Controller.sv

Update Quartus project files

2023-03-30 13:27:59 +02:00

Counter_TestBench.sv

Implement Counter TestBench

2023-03-29 17:08:24 +02:00

Counter.sv

Widthcast increment/decrement in Counter

2023-03-30 13:19:00 +02:00

CPU_nativelink_simulation.rpt

Update Quartus project files

2023-03-29 15:59:23 +02:00

CPU_TestBench.sv

Add empty CPU TestBench

2023-03-30 13:20:24 +02:00

CPU.qsf

Update Quartus project files

2023-03-30 13:27:59 +02:00

CPU.sv

More compact wire definitions in CPU

2023-03-30 13:31:02 +02:00

Decoder_TestBench.sv

Implement CPU "cycle" decoder

2023-03-30 00:21:01 +02:00

Decoder.sv

Implement CPU "cycle" decoder

2023-03-30 00:21:01 +02:00

LogicalUnit_TestBench.sv

Implement TestBench for LogicalUnit

2023-03-29 13:57:15 +02:00

LogicalUnit.sv

Fix sensitivity list of LogicalUnit

2023-03-29 13:54:56 +02:00

Quartus_CPU.qpf

Add Quartus project files

2023-03-27 23:30:38 +02:00

RegisterFile_TestBench.sv

Implement RegisterFile TestBench

2023-03-29 15:59:09 +02:00

RegisterFile.sv

Add permanent reg0 output to RegisterFile

2023-03-30 00:21:31 +02:00

ROM.sv

Implement an example program using ROM

2023-03-29 19:28:32 +02:00

Description

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54 KiB

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SystemVerilog 100%