christoph/quartus-8-bit-cpu
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d57673d5a42d86a6ec7a7b23ef6d3fb18a200f15
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ChUrl d57673d5a4 Fix the ALU sensitivity list
2023-03-29 14:31:45 +02:00
.gitignore
Add .gitignore
2023-03-27 23:29:39 +02:00
ALU.sv
Fix the ALU sensitivity list
2023-03-29 14:31:45 +02:00
ArithmeticUnit_TestBench.sv
Small renaming
2023-03-29 14:31:35 +02:00
ArithmeticUnit.sv
Fix sensitivity list for AithmeticUnit
2023-03-29 13:54:44 +02:00
ConditionalUnit.sv
Implement ALU/Register components
2023-03-23 21:51:50 +01:00
Counter.sv
Implement ALU/Register components
2023-03-23 21:51:50 +01:00
CPU_nativelink_simulation.rpt
Add Quartus project files
2023-03-27 23:30:38 +02:00
CPU.qsf
Add Quartus project files
2023-03-27 23:30:38 +02:00
CPU.qws
Add Quartus project files
2023-03-27 23:30:38 +02:00
LogicalUnit_TestBench.sv
Implement TestBench for LogicalUnit
2023-03-29 13:57:15 +02:00
LogicalUnit.sv
Fix sensitivity list of LogicalUnit
2023-03-29 13:54:56 +02:00
Quartus_CPU.qpf
Add Quartus project files
2023-03-27 23:30:38 +02:00
RegisterFile.sv
Implement ALU/Register components
2023-03-23 21:51:50 +01:00
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SystemVerilog 100%