This website requires JavaScript.
Explore
Help
Sign In
christoph
/
quartus-8-bit-cpu
Watch
1
Fork
0
Code
Activity
20
Commits
1
Branch
0
Tags
f472994fda4f74b48b4b2c63597bbc1a0d68ff48
T
Code
Clone
HTTPS
Tea CLI
Open with VS Code
Open with VSCodium
Open with Intellij IDEA
Download ZIP
Download TAR.GZ
Download BUNDLE
christoph
f472994fda
Add clock input to ALU/ConditionalUnit
2023-03-30 00:21:47 +02:00
.gitignore
Add .gitignore
2023-03-27 23:29:39 +02:00
ALU_TestBench.sv
Add missing "signed" to ALU ports/connections
2023-03-29 15:03:20 +02:00
ALU.sv
Add clock input to ALU/ConditionalUnit
2023-03-30 00:21:47 +02:00
ArithmeticUnit_TestBench.sv
Add missing "signed" to ALU ports/connections
2023-03-29 15:03:20 +02:00
ArithmeticUnit.sv
Add missing "signed" to ALU ports/connections
2023-03-29 15:03:20 +02:00
ConditionalUnit_TestBench.sv
Add missing "signed" to ALU ports/connections
2023-03-29 15:03:20 +02:00
ConditionalUnit.sv
Add clock input to ALU/ConditionalUnit
2023-03-30 00:21:47 +02:00
Counter_TestBench.sv
Implement Counter TestBench
2023-03-29 17:08:24 +02:00
Counter.sv
Parametrize the counter bit width
2023-03-30 00:21:15 +02:00
CPU_nativelink_simulation.rpt
Update Quartus project files
2023-03-29 15:59:23 +02:00
CPU.qsf
Implement Counter TestBench
2023-03-29 17:08:24 +02:00
Decoder_TestBench.sv
Implement CPU "cycle" decoder
2023-03-30 00:21:01 +02:00
Decoder.sv
Implement CPU "cycle" decoder
2023-03-30 00:21:01 +02:00
LogicalUnit_TestBench.sv
Implement TestBench for LogicalUnit
2023-03-29 13:57:15 +02:00
LogicalUnit.sv
Fix sensitivity list of LogicalUnit
2023-03-29 13:54:56 +02:00
Quartus_CPU.qpf
Add Quartus project files
2023-03-27 23:30:38 +02:00
RegisterFile_TestBench.sv
Implement RegisterFile TestBench
2023-03-29 15:59:09 +02:00
RegisterFile.sv
Add permanent reg0 output to RegisterFile
2023-03-30 00:21:31 +02:00
ROM.sv
Implement an example program using ROM
2023-03-29 19:28:32 +02:00
S
Description
No description provided
55
KiB
Languages
SystemVerilog
100%
