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0f7f2742fd
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Implement Counter TestBench
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2023-03-29 17:08:24 +02:00 |
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788cf7566b
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Reformat Counter
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2023-03-29 16:04:13 +02:00 |
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0ba622d9c0
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Update Quartus project files
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2023-03-29 15:59:23 +02:00 |
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6366984b50
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Implement RegisterFile TestBench
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2023-03-29 15:59:09 +02:00 |
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ea5b2c53c2
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Add missing "signed" to ALU ports/connections
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2023-03-29 15:03:20 +02:00 |
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17493586ff
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Implement ALU TestBench
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2023-03-29 14:31:50 +02:00 |
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d57673d5a4
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Fix the ALU sensitivity list
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2023-03-29 14:31:45 +02:00 |
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c07c736de9
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Small renaming
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2023-03-29 14:31:35 +02:00 |
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5128478af7
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Implement TestBench for ArithmeticUnit
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2023-03-29 13:57:23 +02:00 |
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c477148480
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Implement TestBench for LogicalUnit
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2023-03-29 13:57:15 +02:00 |
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57b6316769
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Fix sensitivity list of LogicalUnit
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2023-03-29 13:54:56 +02:00 |
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3d8270b89b
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Fix sensitivity list for AithmeticUnit
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2023-03-29 13:54:44 +02:00 |
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f21d4676c4
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Add Quartus project files
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2023-03-27 23:30:38 +02:00 |
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6c9a027209
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Add .gitignore
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2023-03-27 23:29:39 +02:00 |
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49d1871dfa
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Implement ALU/Register components
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2023-03-23 21:51:50 +01:00 |
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