582c8617d3CPUArchitecture: iterator added to allow iterating over all registers
adrian
2013-01-31 12:19:02 +00:00
e76b7b989bfault-coverage fix due to arch. changes
adrian
2013-01-31 12:18:58 +00:00
ec54a1481cfault-coverage: everything is logged to std::cout, now
adrian
2013-01-31 12:18:54 +00:00
bede34d0c9fault-coverage: intro comment translated
adrian
2013-01-31 12:18:51 +00:00
cb429fddb2typos fixed.
adrian
2013-01-31 12:18:47 +00:00
27128f29acfire-interrupt fix: no more dbgEnableInstrPtrOutput()
adrian
2013-01-31 12:18:44 +00:00
325844876bmh-test-campaign fix due to arch changes
adrian
2013-01-31 12:18:40 +00:00
f5a1213ce1checksum-oostubs-fix due to arch. changes (tested)
adrian
2013-01-31 12:18:37 +00:00
03138b388ananojpeg-fix due to recent architecure changes (compiled but not tested)
adrian
2013-01-31 12:18:32 +00:00
db35166d67- Added and updated documentation for gem5 - Added gem5 configuration used for profiling
friemel
2013-01-30 23:59:32 +00:00
7588834f41Added weather-monitor-gem5 experiment, which is a clone of the weather-monitor experiment with only one run per fail* instance.
friemel
2013-01-30 23:59:28 +00:00
9c62e4a7f2- Added signaling of trap situations needed in the weather-monitor to gem5. - Fixed setting of instruction address for simulator.onMemoryAccess() calls.
friemel
2013-01-30 23:59:24 +00:00
640f5436ccBugfix for regression-test experiment
hellwig
2013-01-30 14:58:18 +00:00
1ce2cd96beregression-test fixes: use new register access syntax
adrian
2013-01-17 13:41:27 +00:00
125914a305BochsRegister.hpp and BochsRegisterIDs.hpp not needed anymore
adrian
2013-01-17 13:41:23 +00:00
03b4356598Bugfix: Let Bochs' trigger breakpoint events even in case of rep-instructions
adrian
2013-01-17 13:41:19 +00:00
0ba62aea8fBoth performance aspects need to respect the argument order of their target methods (pointcuts)
adrian
2013-01-17 13:41:15 +00:00
edf44aec28Bugfixes for aspect headers due to architecure-related changes.
adrian
2013-01-17 13:41:11 +00:00
214bb36b47onIOPort needs to have a ConcreteCPU argument as well; detectCPU() added
adrian
2013-01-17 13:41:07 +00:00
d3cf2359a4FIXMEs and comments updated due to last architecture-related changes
adrian
2013-01-17 13:41:03 +00:00
c4e5ab4f58Fixed reading of instruction pointer for gem5.
friemel
2013-01-16 15:27:10 +00:00
afca00ce0a- Added a define which marks the use of BPRangeListener - Gem5 now has two different implementation for breakpoints. - If only BPSingleListener are used, gem5 Breakpoints are used - If BPRangeListener are used, gem5 calls onBreakpoint() in every simulated instruction
friemel
2013-01-16 15:27:06 +00:00
ac7cec7684ElfReader: Constructor tries to get ELF from ENV FAIL_ELF_PATH
hoffmann
2013-01-15 12:53:49 +00:00
d721ce7041Updated the manual
unzner
2013-01-12 14:00:44 +00:00
0972a22bc9Warn and show hint, if libiberty (needed by demangler) not found
hoffmann
2013-01-11 16:39:03 +00:00
93387c4eecCiAO example experiment: using ENV variable for elf file
hoffmann
2013-01-11 15:57:18 +00:00
2c3996344eUpdated the class diagram
unzner
2013-01-09 22:12:24 +00:00
f936b77083Fixed a bug in ALUInstr and improved logging for RATFlip
unzner
2013-01-08 09:26:11 +00:00
e3bf62aa67Cleaned up campaign source code
unzner
2012-12-24 15:26:36 +00:00
2547021e5d- introduced improved logging in RATFlip - adapted the manual - centralised output conversion
unzner
2012-12-24 12:55:20 +00:00
5b07b4d312Adapted experiment to new framework
unzner
2012-12-22 19:33:50 +00:00
f8aa1237e9Make FailBochs compile again (after changes in r1966).
adrian
2012-12-12 13:08:43 +00:00
2010d4c385Created default x86 CPU interface classes.
adrian
2012-12-12 13:08:39 +00:00
d019f64bf5Export Bochs 64 bit ability (if enabled).
adrian
2012-12-12 13:08:35 +00:00
bc0da74104ArmArchitecture: improve destructor speed by calling clear() instead of erase().
adrian
2012-12-12 13:08:32 +00:00
692172a164ArmArchitecture: set ARM register names (textual ddescription) as well.
adrian
2012-12-12 13:08:28 +00:00
d3ccc75269ArmCPUState: no need to repeat abstract method declarations
adrian
2012-12-12 13:08:24 +00:00
9f53d3348bSimulatorController: no need for return type bool of addCPU().
adrian
2012-12-12 13:08:21 +00:00
25f75b299ccoding style fixed, some FIXMEs and comments added.
adrian
2012-12-12 13:08:17 +00:00
fb4ba0b104hsc-simple: modifications due to architecure changes in r1966.
adrian
2012-12-12 13:08:12 +00:00
4189871920coding-style++
adrian
2012-12-11 15:14:34 +00:00
0799d5dcf1Fixed include name
friemel
2012-12-06 21:22:51 +00:00
378cabd996Updated the manual, corrected some terms and found a bug
unzner
2012-12-06 14:47:42 +00:00
2b36678737Separated Architecture and CPUState classes for ARM/Gem5 (*Architecture will be used in the campaign).
adrian
2012-12-05 13:05:24 +00:00
b981fdcfeacoding style++
adrian
2012-12-05 12:40:34 +00:00
35753cd075coding style++, some TODOs added.
adrian
2012-12-05 12:27:17 +00:00
b052c0494bArchitecture changes (only gem5 implementation right now): - The register manager is gone. It's functionality is now encapsulated in the CPU classes. - For the client, there is the ConcreteCPU class that encapsulates the access to the CPU state (including registers) and architecture details. The correspondig objects for the CPUs inside the simulator can be accessed through the SimulatorController.getCPU() function. - Listener got a new ConcreteCPU* member to filter for which CPU the events should fire. The default NULL is used as wildcard for all aviable CPUs. The events respectively got a ConcreteCPU* member to indicate which CPU really fired the event. - For the server, there is CPUArchitecture to access the architecture details.
friemel
2012-12-02 17:50:46 +00:00
fc1d21fe53Bugfix for server-client communication
hellwig
2012-11-30 18:13:13 +00:00
c689c159fbBugfix of overloaded << operator
hellwig
2012-11-30 16:50:06 +00:00
d7842c2ad7The Jobclient can get several jobs with one request
hellwig
2012-11-30 16:50:02 +00:00
da3b2b8253Adding some documentation
unzner
2012-11-28 14:02:21 +00:00
87ee9df37becos: additional burst fault model
hsc
2012-11-27 17:06:32 +00:00
e130c204aathe injection offset in IDCFlip is now completely left aligned (instead of bytewise left aligned and bitwise right aligned)
unzner
2012-11-27 16:59:05 +00:00
158ac496feAdapted comment to the new TimerListener interface
unzner
2012-11-24 09:48:31 +00:00
1b9583aedeNow the names of the experiments will be consistent with my written work
unzner
2012-11-24 09:37:38 +00:00
5135c79c05TimerListener: microsecond granularity (ms is too coarse)
hsc
2012-11-23 15:35:08 +00:00