coding style fixed, some FIXMEs and comments added.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1974 8c4709b5-6ec9-48aa-a5cd-a96041d1645a

src/core/sal/CPU.hpp

@@ -36,6 +36,7 @@ public:
 	 * @see getType()
 	 */
 	void addRegister(Register* reg);
+	// FIXME: make this protected? no need to modify the register config at runtime...
 	/**
 	 * Retrieves the \a i-th register.
 	 * @return a pointer to the \a i-th register; if \a i is invalid, an

src/core/sal/SimulatorController.hpp

@@ -35,21 +35,20 @@ protected:
 	ListenerManager m_LstList; //!< storage where listeners are being buffered
 	CoroutineManager m_Flows; //!< managed experiment flows
 	MemoryManager *m_Mem; //!< access to memory pool
-	std::vector< ConcreteCPU* > m_CPUs; //!< list of cpus in the target system
+	std::vector<ConcreteCPU*> m_CPUs; //!< list of CPUs in the target system
 	friend class ListenerManager; //!< "outsources" the listener management
 public:
-	SimulatorController()
-		: m_Mem(NULL) { }
-	SimulatorController(MemoryManager* mem)
-		: m_Mem(mem) { }
+	SimulatorController() : m_Mem(NULL) { }
+	SimulatorController(MemoryManager* mem) : m_Mem(mem) { }
 	virtual ~SimulatorController()
 	{
-		std::vector< ConcreteCPU* >::iterator it = m_CPUs.begin();
-		while(it != m_CPUs.end())
-		{
+		std::vector<ConcreteCPU*>::iterator it = m_CPUs.begin();
+		while (it != m_CPUs.end()) {
 			delete *it;
 			it = m_CPUs.erase(it);
 		}
+		// FIXME: This expects the "ConcreteCPU" objects to be allocated on the heap...
+		// This should be part of the derived class...?
 	}
 	/**
 	 * @brief Initialization function each implementation needs to call on
@@ -146,8 +145,9 @@ public:
 	 */
 	bool addCPU(ConcreteCPU* cpu);
 	/**
-	 * Gets the CPU with the provided id.
-	 * @oaram id the id of the CPU to get
+	 * Gets the CPU with the provided \c id.
+	 * @param id the id of the CPU to get
+	 * @return a reference to the requested CPU object
 	 */
 	ConcreteCPU& getCPU(size_t id) const;
 	/**

src/core/sal/arm/Architecture.cc

@@ -20,8 +20,8 @@ void ArmArchitecture::fillRegisterList()
 
 ArmArchitecture::~ArmArchitecture()
 {
-	std::vector< Register* >::iterator it = m_Registers.begin();
-	while (it != m_Registers.end()) {
+	for (std::vector<Register*>::iterator it = m_Registers.begin();
+		 it != m_Registers.end(); it++)
 		delete *it;
 		it = m_Registers.erase(it);
 	}

src/core/sal/arm/Architecture.hpp

@@ -19,6 +19,10 @@ private:
 	void fillRegisterList();
 };
 
+/**
+ * \enum GPRegIndex
+ * TODO.
+ */
 enum GPRegIndex {
 	RI_R0,
 	RI_R1,

src/core/sal/bochs/BochsController.hpp

@@ -43,7 +43,9 @@ private:
 	BX_CPU_C *m_CPUContext; //!< Additional information that is passed on occurence of a BPEvent
 	bxInstruction_c *m_CurrentInstruction; //!< dito.
 public:
-	// Initialize the controller.
+	/**
+	 * Initialize the controller, i.e. add the number of simulated CPUs.
+	 */
 	BochsController();
 	~BochsController();
 	/* ********************************************************************

src/core/sal/bochs/BochsRegister.hpp

@@ -22,8 +22,7 @@ public:
 	/**
 	 * Constructs a new register object.
 	 * @param id the global unique id
-	 * @param width width of the register (8, 16, 32 or 64 bit should
-	 *        suffice)
+	 * @param width width of the register (8, 16, 32 or 64 bit should suffice)
 	 * @param link pointer to bochs interal register memory
 	 * @param t type of the register
 	 */

src/core/sal/gem5/Gem5ArmCPU.hpp

@@ -11,7 +11,7 @@ namespace fail {
 class Gem5ArmCPU : public ArmArchitecture, public ArmCPUState {
 public:
 	// TODO: comments
-	Gem5ArmCPU(unsigned int id, System* system) : m_Id(id), m_System(system) {}
+	Gem5ArmCPU(unsigned int id, System* system) : m_Id(id), m_System(system) { }
 	regdata_t getRegisterContent(Register* reg);
 	void setRegisterContent(Register* reg, regdata_t value);
 
@@ -20,7 +20,6 @@ public:
 	address_t getLinkRegister();
 
 	unsigned int getId() { return m_Id; }
-
 private:
 	unsigned int m_Id;
 	System* m_System;