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Fixed reading of instruction pointer for gem5.

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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2004 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
friemel
2013-01-16 15:27:10 +00:00
parent afca00ce0a
commit c4e5ab4f58
2 changed files with 13 additions and 2 deletions
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9
src/core/sal/arm/Architecture.cc
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@ -18,9 +18,16 @@ void ArmArchitecture::fillRegisterList()
// Build and set the register name:
std::stringstream sstr;
sstr << "R" << i+1;
reg->setName(str.str());
// FIXME This doesn't work because no matching setName is found.
// Not sure why this happens.
//reg->setName(sstr.str());
addRegister(reg);
}
// Instruction Pointer
Register *reg = new Register(RI_IP, RT_IP, 32);
reg->setName("IP");
addRegister(reg);
}
ArmArchitecture::~ArmArchitecture()

6
src/core/sal/gem5/Gem5ArmCPU.cc
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@ -6,6 +6,10 @@ regdata_t Gem5ArmCPU::getRegisterContent(Register* reg)
{
switch (reg->getType()) {
case RT_GP:
if (reg->getIndex() == 15) {
return m_System->getThreadContext(m_Id)->pcState().pc();
}
return m_System->getThreadContext(m_Id)->readIntReg(reg->getIndex());
case RT_FP:
@ -15,7 +19,7 @@ regdata_t Gem5ArmCPU::getRegisterContent(Register* reg)
return m_System->getThreadContext(m_Id)->readMiscReg(reg->getIndex());
case RT_IP:
return getRegisterContent(getRegister(RI_IP));
return m_System->getThreadContext(m_Id)->pcState().pc();
}
// This shouldn't be reached if a valid register is passed