From c4e5ab4f588f0faa1f9b6bfd2d20ed7269bb108c Mon Sep 17 00:00:00 2001
From: friemel <friemel@8c4709b5-6ec9-48aa-a5cd-a96041d1645a>
Date: Wed, 16 Jan 2013 15:27:10 +0000
Subject: [PATCH] Fixed reading of instruction pointer for gem5.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2004 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
---
 src/core/sal/arm/Architecture.cc | 9 ++++++++-
 src/core/sal/gem5/Gem5ArmCPU.cc  | 6 +++++-
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/src/core/sal/arm/Architecture.cc b/src/core/sal/arm/Architecture.cc
index ac7df412..bb84d130 100644
--- a/src/core/sal/arm/Architecture.cc
+++ b/src/core/sal/arm/Architecture.cc
@@ -18,9 +18,16 @@ void ArmArchitecture::fillRegisterList()
 		// Build and set the register name:
 		std::stringstream sstr;
 		sstr << "R" << i+1;
-		reg->setName(str.str());
+		// FIXME This doesn't work because no matching setName is found.
+		// Not sure why this happens.
+		//reg->setName(sstr.str());
 		addRegister(reg);
 	}
+
+	// Instruction Pointer
+	Register *reg = new Register(RI_IP, RT_IP, 32);
+	reg->setName("IP");
+	addRegister(reg);
 }
 
 ArmArchitecture::~ArmArchitecture()
diff --git a/src/core/sal/gem5/Gem5ArmCPU.cc b/src/core/sal/gem5/Gem5ArmCPU.cc
index 1b2ccabc..c457539b 100644
--- a/src/core/sal/gem5/Gem5ArmCPU.cc
+++ b/src/core/sal/gem5/Gem5ArmCPU.cc
@@ -6,6 +6,10 @@ regdata_t Gem5ArmCPU::getRegisterContent(Register* reg)
 {
 	switch (reg->getType())	{
 	case RT_GP:
+		if (reg->getIndex() == 15) {
+			return m_System->getThreadContext(m_Id)->pcState().pc();
+		}
+			
 		return m_System->getThreadContext(m_Id)->readIntReg(reg->getIndex());
 			
 	case RT_FP:
@@ -15,7 +19,7 @@ regdata_t Gem5ArmCPU::getRegisterContent(Register* reg)
 		return m_System->getThreadContext(m_Id)->readMiscReg(reg->getIndex());
 
 	case RT_IP:
-		return getRegisterContent(getRegister(RI_IP));
+		return m_System->getThreadContext(m_Id)->pcState().pc();
 	}
 
 	// This shouldn't be reached if a valid register is passed