Created default x86 CPU interface classes.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1980 8c4709b5-6ec9-48aa-a5cd-a96041d1645a

src/core/sal/x86/Architecture.cc

@@ -0,0 +1,54 @@
+#include "Architecture.hpp"
+#include "../Register.hpp"
+#include <sstream>
+
+namespace fail {
+
+X86Architecture::X86Architecture()
+{
+	// -------------------------------------
+	// Add the general purpose register:
+  #ifdef SIM_SUPPORT_64
+	// -- 64 bit register --
+  	const  std::string names[] = { "RAX", "RCX", "RDX", "RBX", "RSP", "RBP", "RSI", "RDI", "R8",
+  	                               "R9", "R10", "R11", "R12", "R13", "R14", "R15" };
+	for (unsigned short i = 0; i < 16; i++) {
+		Register* pReg = new Register(i, RT_GP, 64);
+		pReg->setName(names[i]);
+		addRegister(pReg);
+	}
+  #else
+  	// -- 32 bit register --
+  	const std::string names[] = { "EAX", "ECX", "EDX", "EBX", "ESP", "EBP", "ESI", "EDI" };
+	for (unsigned short i = 0; i < 8; i++) {
+		Register* pReg = new Register(i, RT_GP, 32);
+		pReg->setName(names[i]);
+		addRegister(pReg);
+	}
+  #endif // SIM_SUPPORT_64
+	// -------------------------------------
+	// Add the program counter (PC) register:
+  #ifdef SIM_SUPPORT_64
+	Register* pPCReg = new Register(RID_PC, RT_IP, 64);
+	pPCReg->setName("RIP");
+  #else
+    Register* pPCReg = new Register(RID_PC, RT_IP, 32);
+	pPCReg->setName("EIP");
+  #endif // SIM_SUPPORT_64
+	addRegister(pPCReg);
+    // -------------------------------------
+	// Add the status register (EFLAGS):
+	Register* pFlagReg = new Register(RID_FLAGS, RT_ST, 32);
+	pFlagReg->setName("EFLAGS");
+	addRegister(pFlagReg);
+}
+
+X86Architecture::~X86Architecture()
+{
+	for (std::vector<Register*>::iterator it = m_Registers.begin();
+		 it != m_Registers.end(); it++)
+		delete *it;
+	m_Registers.clear();
+}
+
+} // end-of-namespace: fail

src/core/sal/x86/Architecture.hpp

@@ -0,0 +1,57 @@
+#ifndef __X86_ARCHITECTURE_HPP__
+  #define __X86_ARCHITECTURE_HPP__
+
+#include "../CPU.hpp"
+#include "../CPUState.hpp"
+#include "../SALConfig.hpp"
+
+// TODO: Remove BochsRegister.* files ... shouldn't be required anymore...
+
+namespace fail {
+
+/**
+ * \class X86Architecture
+ * This class adds x86 specific functionality to the base architecture.
+ * This can be used for every simulator backend that runs on x86.
+ */
+class X86Architecture : public CPUArchitecture {
+public:
+	X86Architecture();
+	~X86Architecture();
+};
+
+/**
+ * \enum GPRegisterId
+ * Symbolic identifier to access the x86 general purpose register
+ * (within the corresponding GP set). This enumeration is extended
+ * in case the activated simulator has 64 bit ability.
+ */
+enum GPRegisterId {
+ #ifdef SIM_SUPPORT_64 // 64 bit register id's:
+	RID_RAX = 0, RID_RCX, RID_RDX, RID_RBX, RID_RSP, RID_RBP, RID_RSI, RID_RDI,
+	RID_R8, RID_R9, RID_R10, RID_R11, RID_R12, RID_R13, RID_R14, RID_R15,
+ #else // 32 bit register id's:
+	RID_EAX = 0, RID_ECX, RID_EDX, RID_EBX, RID_ESP, RID_EBP, RID_ESI, RID_EDI,
+ #endif // common register id's (independent of the current register width):
+    RID_CAX = 0, RID_CCX, RID_CDX, RID_CBX, RID_CSP, RID_CBP, RID_CSI, RID_CDI,
+    RID_LAST_GP_ID
+};
+// FIXME: RID_RSP/RID_ESP/RID_CSP is not a GP register but this definition makes
+// it much easier to map the id to Bochs' internal register id.
+
+/**
+ * \enum PCRegisterId
+ * Symbolic identifier to access the program counter (PC, aka
+ * instruction pointer, in short IP) register.
+ */
+enum PCRegisterId { RID_PC = RID_LAST_GP_ID, RID_LAST_PC_ID };
+
+/**
+ * \enum FlagsRegisterId
+ * Symbolic identifier to access the flags register.
+ */
+enum FlagsRegisterId { RID_FLAGS = RID_LAST_PC_ID };
+
+} // end-of-namespace: fail
+
+#endif // __X86_ARCHITECTURE_HPP__

src/core/sal/x86/CPUState.hpp

@@ -0,0 +1,29 @@
+#ifndef __X86_CPU_STATE_HPP__
+  #define __X86_CPU_STATE_HPP__
+
+#include "../CPU.hpp"
+#include "../CPUState.hpp"
+
+namespace fail {
+
+/**
+ * \class X86CPUState
+ * TODO.
+ */
+class X86CPUState : public CPUState {
+public:
+	/**
+	 * Returns the current content of the base pointer register.
+	 * @return the current (e)bp
+	 */
+	virtual address_t getBasePointer() = 0;
+	/**
+	 * Returns the current (E)FLAGS.
+	 * @return the current (E)FLAGS processor register content
+	 */
+	virtual regdata_t getFlagsRegister() = 0;
+};
+
+} // end-of-namespace: fail
+
+#endif // __X86_CPU_STATE_HPP__