ff2dc189ce
Correction of commit 2014
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2019 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-24 11:26:26 +00:00
bcb48344ea
revert "bugfix: typo in CMakeLists.txt (CLIENT_JOB_LIMIT -> CLIENT_JOB_LIMIT_SEC)"
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This reverts commit 270d37e929e584786fc40a336a9f73962182648f.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2018 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-24 11:21:16 +00:00
ed3e81d290
bugfix: typo in CMakeLists.txt (CLIENT_JOB_LIMIT -> CLIENT_JOB_LIMIT_SEC)
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2017 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-24 11:05:33 +00:00
ce9db1fdb3
hsc-simple: experiment should not terminate because we want to see Bochs' output (3 * 3 = 666 :-))
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2016 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-24 10:00:49 +00:00
ff7d2ec076
experiment.cc (weather-monitor) restored
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The file was accidentally overwritten during last commit... :/
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2015 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-23 14:32:56 +00:00
00f809231f
Code cleanup for commit 1963-1965
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2014 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-23 14:22:05 +00:00
0cbb38d605
VEZS experiment: cleanup.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2013 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-22 10:03:18 +00:00
1ce2cd96be
regression-test fixes: use new register access syntax
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The golden-run image of the regression test needs to be updated in order to cope with the bugfix for breakpoint events in rep-instructions.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2011 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-17 13:41:27 +00:00
125914a305
BochsRegister.hpp and BochsRegisterIDs.hpp not needed anymore
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The includes of these headers have already been removed from the experiments. In the current code, the content of the header BochsRegister.hpp is rather simply copied to x86/Architecture.hpp. It is therefore necessary to revisit the code soon (especially the FIXME related to register IDs).
Another problem is that there is no generalization of register IDs. Thus, all experiments are currently specific to a concrete architecture (which is not desired).
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2010 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-17 13:41:23 +00:00
03b4356598
Bugfix: Let Bochs' trigger breakpoint events even in case of rep-instructions
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This reverts the solution of a former commit (see git hash e1f6601d8494bcb002e89543a9334e053f0e69d3). All additional changes proposed in that commit have been deleted and the major work is now done by the aspect header BreakRepeatInstr.ah: It ensures the condition in the methods repeat() and repeat_ZF() if (BX_CPU_THIS_PTR async_event) ... to be always true which causes Bochs to leave these methods immediately. This, in turn, involves a call to defineCPULoopJointPoint(), yielding a breakpoint event in Fail.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2009 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-17 13:41:19 +00:00
0ba62aea8f
Both performance aspects need to respect the argument order of their target methods (pointcuts)
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Additionaly, the CPU object is passed to the Event object construction in ordner to set the trigger CPU ptr (in PerfVector{Watchpoints,Breakpoints}::gather()) properly.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2008 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-17 13:41:15 +00:00
edf44aec28
Bugfixes for aspect headers due to architecure-related changes.
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Now, each aspect calls it's corresponding event headler by providing the new CPU object pointer as well.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2007 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-17 13:41:11 +00:00
214bb36b47
onIOPort needs to have a ConcreteCPU argument as well; detectCPU() added
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detectCPU() allows us to easily retrieve the current Fail-CPU object which is a regular use case in the aspect headers, now. (Another solution would be a slice in the Bochs CPU class which inserts a reference to the Fail CPU object. Maybe we 'll implement this at a later point.)
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2006 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-17 13:41:07 +00:00
d3cf2359a4
FIXMEs and comments updated due to last architecture-related changes
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2005 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-17 13:41:03 +00:00
c4e5ab4f58
Fixed reading of instruction pointer for gem5.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2004 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-16 15:27:10 +00:00
afca00ce0a
- Added a define which marks the use of BPRangeListener
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- Gem5 now has two different implementation for breakpoints.
- If only BPSingleListener are used, gem5 Breakpoints are used
- If BPRangeListener are used, gem5 calls onBreakpoint() in every simulated instruction
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2003 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-16 15:27:06 +00:00
ac7cec7684
ElfReader: Constructor tries to get ELF from ENV FAIL_ELF_PATH
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2002 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-15 12:53:49 +00:00
d721ce7041
Updated the manual
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1999 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-12 14:00:44 +00:00
0972a22bc9
Warn and show hint, if libiberty (needed by demangler) not found
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1996 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-11 16:39:03 +00:00
93387c4eec
CiAO example experiment: using ENV variable for elf file
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1994 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-11 15:57:18 +00:00
2c3996344e
Updated the class diagram
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1992 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-09 22:12:24 +00:00
f936b77083
Fixed a bug in ALUInstr and improved logging for RATFlip
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1991 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-08 09:26:11 +00:00
e3bf62aa67
Cleaned up campaign source code
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1989 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-24 15:26:36 +00:00
2547021e5d
- introduced improved logging in RATFlip
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- adapted the manual
- centralised output conversion
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1988 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-24 12:55:20 +00:00
5b07b4d312
Adapted experiment to new framework
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1987 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-22 19:33:50 +00:00
02c27b58c6
Removed narrowing conversion
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1986 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-22 18:30:50 +00:00
4051c0f4e9
ElfReader: Added support for de/mangled symbols
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See vezs-example experiment for usage.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1985 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-21 12:12:25 +00:00
e5323abcf9
Preparing CiAO experiments
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1984 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-20 22:37:29 +00:00
5a3a66da25
Reverse search getNameByAddress.
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Implemented with the help of boost bimap.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1983 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-20 22:06:46 +00:00
f8aa1237e9
Make FailBochs compile again (after changes in r1966).
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For now, only breakpoints are working. Other event sources need to be revised, too.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1981 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:43 +00:00
2010d4c385
Created default x86 CPU interface classes.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1980 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:39 +00:00
d019f64bf5
Export Bochs 64 bit ability (if enabled).
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This is required to add the architecture-dependent registers.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1979 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:35 +00:00
bc0da74104
ArmArchitecture: improve destructor speed by calling clear() instead of erase().
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1978 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:32 +00:00
692172a164
ArmArchitecture: set ARM register names (textual ddescription) as well.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1977 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:28 +00:00
d3ccc75269
ArmCPUState: no need to repeat abstract method declarations
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(...if they have already been defined in the base class).
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1976 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:24 +00:00
9f53d3348b
SimulatorController: no need for return type bool of addCPU().
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1975 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:21 +00:00
25f75b299c
coding style fixed, some FIXMEs and comments added.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1974 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:17 +00:00
fb4ba0b104
hsc-simple: modifications due to architecure changes in r1966.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1973 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:12 +00:00
4189871920
coding-style++
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1972 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-11 15:14:34 +00:00
0799d5dcf1
Fixed include name
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1971 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-06 21:22:51 +00:00
378cabd996
Updated the manual, corrected some terms and found a bug
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1970 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-06 14:47:42 +00:00
2b36678737
Separated Architecture and CPUState classes for ARM/Gem5 (*Architecture will be used in the campaign).
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1969 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-05 13:05:24 +00:00
b981fdcfea
coding style++
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1968 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-05 12:40:34 +00:00
35753cd075
coding style++, some TODOs added.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1967 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-05 12:27:17 +00:00
b052c0494b
Architecture changes (only gem5 implementation right now):
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- The register manager is gone. It's functionality is now encapsulated in the
CPU classes.
- For the client, there is the ConcreteCPU class that encapsulates the access
to the CPU state (including registers) and architecture details. The
correspondig objects for the CPUs inside the simulator can be accessed
through the SimulatorController.getCPU() function.
- Listener got a new ConcreteCPU* member to filter for which CPU the events
should fire. The default NULL is used as wildcard for all aviable CPUs. The
events respectively got a ConcreteCPU* member to indicate which CPU really
fired the event.
- For the server, there is CPUArchitecture to access the architecture details.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1966 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-02 17:50:46 +00:00
fc1d21fe53
Bugfix for server-client communication
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1965 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-11-30 18:13:13 +00:00
c689c159fb
Bugfix of overloaded << operator
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1964 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-11-30 16:50:06 +00:00
d7842c2ad7
The Jobclient can get several jobs with one request
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1963 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-11-30 16:50:02 +00:00
da3b2b8253
Adding some documentation
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1962 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-11-28 14:02:21 +00:00
87ee9df37b
ecos: additional burst fault model
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1961 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-11-27 17:06:32 +00:00
