christoph/fail
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eb17e9ef8260b2799f8edf7de86e2d8fa97da85c
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160 Commits

Author SHA1 Message Date
Horst Schirmeier
eb17e9ef82 core/sal: move command-line parameter passing to SC::startup() 2013-03-14 22:29:43 +01:00
Horst Schirmeier
422db3e21d core/util: indirection to CommandLine class added to make bochs compile 
If CommandLine.hpp and (indirectly) optionparser.h is #included in
FailBochsInit.ah, bochs compilation fails (for, e.g., gui/x.cc, at least
on Debian 6).
 2013-03-14 18:13:13 +01:00
Christian Dietrich
ad3c185b61 core/util: Added CommandLine interface (for bochs) 2013-03-11 15:29:26 +01:00
Christian Dietrich
c1f32f5a98 ElfReader: add some convenience functions 2013-03-11 15:29:25 +01:00
Martin Hoffmann
f586351e79 T32: Dissassembler to evaluate memory instructions. 
For the T32 variant we have to evaluate the memory
access instruction to find out, which memory address
was accessed.

Dissassmbly by OpenOCDs arm_disassembler.hpp/.cc:
- fine for ARM / Thumb1
- needs fixes for Thumb2 :( (currently doing that..)
 2013-03-11 12:17:53 +01:00
Martin Hoffmann
1fe1dbb3ed util: Added disassembler using objdump tool. 
The disassembler disassembles an elf file with
an external objdump tool.
The architecture specific objdump must be configured
via cmake (ARCH_TOOL_PREFIX), e.g. arm-none-eabi- for
arm-none-eabi-objdump.
 2013-03-05 21:20:25 +01:00
Martin Hoffmann
3501050548 T32: FailT32 support for Cortex-M3 
Currently working:
 - Connect/Disconnect, Read CPU info
 - CMM Script generation and T32 startup via cmake (make runt32)
 - Read/Write Register, Read Program Pointer
 - Read/Write Memory
 - Single Breakpoint
 - Setting Memory Breakpoint

TODO:
 - Fix mock aspect for T32_GetRam.
 - Fix Thumb2 bit in function addresses from ELFReader
 - Evaluate memory breakpoint hit
 2013-03-01 12:47:32 +01:00
Martin Hoffmann
447411da9a T32: Evalute memory map, RangeListener, MemAccess 2013-02-21 12:32:55 +01:00
hoffmann
205c7ec919 T32: Breakpoint test code 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2107 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-16 23:05:07 +00:00
hoffmann
6761268d93 T32: Added BPSingle, central T32 specific api constants 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2106 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-16 23:05:04 +00:00
hoffmann
2e16b8873b T32: Memory access. 
Still not tested on real T32.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2105 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-16 22:05:02 +00:00
hoffmann
d86d18bced T32: Code cleanup. 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2104 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-16 22:05:00 +00:00
hoffmann
39a6415001 T32: Integrated Register read/write calls 
* Tested without connected Lauterbach.
  T32_* functions are mocked via aspect.

* New target t32cli, for sending T32 command cia cli. (for testing)

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2103 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-15 18:06:02 +00:00
adrian
bf9e111b9f no need for a separate fillRegisterList() method(only called once) 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2086 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-14 14:45:30 +00:00
adrian
e81517645f doc for X86CPUState added, FIXME removed 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2085 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-14 14:45:26 +00:00
adrian
3cc40e62c7 A few CPUState-related methods should be const (getter) 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2084 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-14 14:45:22 +00:00
adrian
accfba8237 coding-style++, gem5 code doc added 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2083 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-14 14:45:18 +00:00
adrian
c8a9039f36 #error msg for gem5 + x85 added (not supported yet) 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2082 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-14 14:45:13 +00:00
adrian
7f587d461c ArmArchitecture::fillRegisterList(): set textual register name appropriately 
For some reasons, the compiler cannot find a matching Register::setName(const std::string&) although it is implemented in sal/Register.cc. The work around fixes this issue.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2077 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-07 14:17:49 +00:00
adrian
f96f4dd360 typo-fix 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2075 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-07 10:43:07 +00:00
hoffmann
3307987895 Added missing virtual Destructor, fixes gcc warning 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2068 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-07 00:51:19 +00:00
hoffmann
94214063ac Fixed whitespaces. 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2067 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-07 00:51:14 +00:00
adrian
d9808c0fca DEBUG flag in BochsController not needed anymore 
It is a remnant of former times. ;-)

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2065 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-06 15:39:54 +00:00
adrian
5c4b132550 ~SimulatorController: do not free ConcreteCPU object ptr in the base class 
In fact, delete should be called in the destructor of each derived class (BochsController and Gem5Controller at the moment).

Additionally, this is the reason why ~SimulatorController is declared as virtual.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2064 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-06 15:39:50 +00:00
adrian
552a5fb4ac coding-style++, comments++, FIXMEs++ 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2063 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-06 15:39:46 +00:00
adrian
38b7064189 Make CPUArchitecure::addRegister protected: no need to modify the register config in an experiment 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2062 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-06 15:39:41 +00:00
hellwig
e98b18e678 Breakpoint aspects updated 
The aspects respond to the new CONFIG_EVENT_BREAKPOINT_RANGE flag now.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2040 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-31 14:32:14 +00:00
hellwig
ac3702b5e8 Rename: CONFIG_EVENT_RANGEBREAKPOINTS -> CONFIG_EVENT_BREAKPOINTS_RANGE 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2037 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-31 14:32:03 +00:00
adrian
582c8617d3 CPUArchitecture: iterator added to allow iterating over all registers 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2036 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-31 12:19:02 +00:00
adrian
cb429fddb2 typos fixed. 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2032 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-31 12:18:47 +00:00
friemel
db35166d67 - Added and updated documentation for gem5 
- Added gem5 configuration used for profiling

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2027 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-30 23:59:32 +00:00
adrian
125914a305 BochsRegister.hpp and BochsRegisterIDs.hpp not needed anymore 
The includes of these headers have already been removed from the experiments. In the current code, the content of the header BochsRegister.hpp is rather simply copied to x86/Architecture.hpp. It is therefore necessary to revisit the code soon (especially the FIXME related to register IDs).

Another problem is that there is no generalization of register IDs. Thus, all experiments are currently specific to a concrete architecture (which is not desired).

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2010 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-17 13:41:23 +00:00
adrian
03b4356598 Bugfix: Let Bochs' trigger breakpoint events even in case of rep-instructions 
This reverts the solution of a former commit (see git hash e1f6601d8494bcb002e89543a9334e053f0e69d3). All additional changes proposed in that commit have been deleted and the major work is now done by the aspect header BreakRepeatInstr.ah: It ensures the condition in the methods repeat() and repeat_ZF() if (BX_CPU_THIS_PTR async_event) ... to be always true which causes Bochs to leave these methods immediately. This, in turn, involves a call to defineCPULoopJointPoint(), yielding a breakpoint event in Fail.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2009 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-17 13:41:19 +00:00
adrian
0ba62aea8f Both performance aspects need to respect the argument order of their target methods (pointcuts) 
Additionaly, the CPU object is passed to the Event object construction in ordner to set the trigger CPU ptr (in PerfVector{Watchpoints,Breakpoints}::gather()) properly.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2008 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-17 13:41:15 +00:00
adrian
edf44aec28 Bugfixes for aspect headers due to architecure-related changes. 
Now, each aspect calls it's corresponding event headler by providing the new CPU object pointer as well.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2007 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-17 13:41:11 +00:00
adrian
214bb36b47 onIOPort needs to have a ConcreteCPU argument as well; detectCPU() added 
detectCPU() allows us to easily retrieve the current Fail-CPU object which is a regular use case in the aspect headers, now. (Another solution would be a slice in the Bochs CPU class which inserts a reference to the Fail CPU object. Maybe we 'll implement this at a later point.)

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2006 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-17 13:41:07 +00:00
adrian
d3cf2359a4 FIXMEs and comments updated due to last architecture-related changes 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2005 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-17 13:41:03 +00:00
friemel
c4e5ab4f58 Fixed reading of instruction pointer for gem5. 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2004 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-16 15:27:10 +00:00
friemel
afca00ce0a - Added a define which marks the use of BPRangeListener 
- Gem5 now has two different implementation for breakpoints.
  - If only BPSingleListener are used, gem5 Breakpoints are used
  - If BPRangeListener are used, gem5 calls onBreakpoint() in every simulated instruction

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2003 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-16 15:27:06 +00:00
adrian
f8aa1237e9 Make FailBochs compile again (after changes in r1966). 
For now, only breakpoints are working. Other event sources need to be revised, too.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1981 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2012-12-12 13:08:43 +00:00
adrian
2010d4c385 Created default x86 CPU interface classes. 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1980 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2012-12-12 13:08:39 +00:00
adrian
d019f64bf5 Export Bochs 64 bit ability (if enabled). 
This is required to add the architecture-dependent registers.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1979 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2012-12-12 13:08:35 +00:00
adrian
bc0da74104 ArmArchitecture: improve destructor speed by calling clear() instead of erase(). 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1978 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2012-12-12 13:08:32 +00:00
adrian
692172a164 ArmArchitecture: set ARM register names (textual ddescription) as well. 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1977 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2012-12-12 13:08:28 +00:00
adrian
d3ccc75269 ArmCPUState: no need to repeat abstract method declarations 
(...if they have already been defined in the base class).

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1976 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2012-12-12 13:08:24 +00:00
adrian
9f53d3348b SimulatorController: no need for return type bool of addCPU(). 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1975 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2012-12-12 13:08:21 +00:00
adrian
25f75b299c coding style fixed, some FIXMEs and comments added. 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1974 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2012-12-12 13:08:17 +00:00
friemel
0799d5dcf1 Fixed include name 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1971 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2012-12-06 21:22:51 +00:00
adrian
2b36678737 Separated Architecture and CPUState classes for ARM/Gem5 (*Architecture will be used in the campaign). 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1969 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2012-12-05 13:05:24 +00:00
adrian
b981fdcfea coding style++ 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1968 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2012-12-05 12:40:34 +00:00