Commit Graph

40 Commits

Author SHA1 Message Date
d3d2faf680 globally rename Fail* to FAIL*
Change-Id: Ief2cb687cc69dd92c2e04f9314f0f1347e0a84ed
2016-07-26 17:41:32 +02:00
c069e87c6f gem5: adapt to changed SimulatorController iface
This quick fix is necessary to let gem5 compile again.  Instead of passing
NULL to onInterrupt(), a proper fix should pass the currently active
ConcreteCPU instance.

Change-Id: Ie4322fd98cb7b12309a21a2dd431f9bdc84efaf8
2015-08-06 16:33:19 +02:00
cafbe1df75 bochs: #undef all macros from dis_tables.h
The file dis_tables.h does define several macros with very generic
names (I1, I2). These macros interfere in certain situations with the
boost headers. Therefore, we simply undef all those xmacro arguments,
like it should be done.

Change-Id: Iddf74f04ec016a7ea5de5a66543b670a8992a5d6
2014-10-21 17:06:12 +02:00
b60e1c0c66 gem5: campaigns are now running without interruption
This change introduces a fake iobus device into gem5 to prevent
it from crashing on bogus I/O memory accesses.

Change-Id: Ie69e3191bdd917cc681269852937a5a3820a93fb
2014-06-05 17:14:11 +02:00
b1c9c295ca bochs: catch division by zero in floppy controller
This change fixes another Bochs crash in the floppy controller,
triggered by one out of 670 million experiments in my current
campaign.

Change-Id: I8a2ff78c9d2c8fca12eefb97f508bc213373bbfa
2014-04-27 19:04:05 +02:00
5fbf13d07d gem5: TrapListener implemented
The TrapListener works like in Bochs.
Instead of a number to a trap the offset is returned for GEM5.
See:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0211h/Babfeega.html

Conflicts:
	simulators/gem5/src/cpu/simple/atomic.cc

Change-Id: Ia8b2083e3c16315d9c577150f14f16995494b2e6
2014-01-21 16:09:08 +01:00
f41247b143 gem5: don't count instruction fetch as mem access
Change-Id: I6ea9811c132ef7c235d5a03486ca08afc842b51f
2014-01-06 15:54:02 +01:00
45e0b41022 gem5: restore works now
The function restore(PATH) can now be used to restore a checkpoint.

Change-Id: I25faf9f6335261d2b3ade4185eae93983ece9f97
2013-11-13 17:15:19 +01:00
5e238cc3f9 gem5 startup script: revisited fs.py to get rid of ARM linux images
In former versions, the aforementioned image was 'required' to run
gem5 although it wasn't actually used at all. With the new python
script fail_fs.py, it suffices to start gem5 on a target foo.elf by
simply typing $ ../scripts/run-gem5.sh path/to/target/foo.elf

Change-Id: I7f48460e50d48d55fe22f2381e2ae8aec8510233
2013-08-21 12:05:16 +02:00
618fdb8e77 gem5 buildsys: compiler flag fixed due to newer gcc version
(Debian 7.1 comes with gcc 4.7.2) However, we are faking a gcc v4.4.5
but the gem5 build system only adds the '-Wno-unused-but-set-variable'
flag in case of a gcc >= v4.6. Now, this flag will always be appended.
(Older gcc versions should ignore the flag or emit a warning but will
continue to run.)

Change-Id: I7021e08019951375c7e8b56d0f875191f904971d
2013-07-31 17:08:14 +02:00
aecb353087 cmake: gem5-related build system updates
The build system now allows incremental gem5 builds. Unfortunately,
the current solution always requires re-linking the executable.
Without the enforcement of re-linking, the fail code will be rebuilt
but not linked into gem5.

The number of cores for building gem5 is derived from /proc/cpuinfo.
As before, only the gem5.debug configuration is supported.

Change-Id: Ib13b15d1ecd62196eb251e0fd00953f4eb052feb
2013-07-04 15:01:22 +02:00
f92557c2c2 gem5: codebase patched to compile with ag++
This changes allows us to compile the gem5 simulator with ag++. It
was tested with ag++ v0.8, built Apr 18 2013. Most of the changes
are preprocessor directives like #ifndef __puma which have been
inserted into the gem5 code. Unfortunately, a python script and a
SWIG input file have been patched, too.
Additionally, the CMake file has been updated. A single call to
"make" now invokes the ag++ (instead of the g++) compiler front
end. The new CMake target "gem5-allclean" should be used to clean
the current project when building FailGem5. In addition to cleaning
the Fail build directory, it also invokes "scons -c" in the gem5
build directory; that is, gem5 is cleaned as well.

Change-Id: I20a92f025f34f626b81e30f2c873baeba189f83b
2013-05-16 15:35:28 +02:00
a3cafbd78b Revisited breakpoint implementation of gem5.
Now, the gem5 implementation equals the Bochs variant. Note that its
necessary to enable CONFIG_EVENTS_BREAKPOINTS_RANGE in order to use
range breakpoints.
In addition, gem5 distinguishes between macro- and microops. With the
new implemenation, onBreakpoint is only called when a macroop changes.

Change-Id: Ib86d1802fc70c20d22ca1a1ece0e8d1221b2e7db
2013-04-24 13:06:44 +02:00
2910e8462e Merge "Removed OVP-related (source) files/code (backend discarded)." 2013-04-23 14:27:02 +02:00
5feebab5ab bochs: fix parsing ips values > 2^31
Change-Id: If331ad7aeedf04c1a62a9bca4bbe74021b5fccd5
2013-04-22 14:24:50 +02:00
03bcf7bfc8 Removed OVP-related (source) files/code (backend discarded).
Change-Id: Ibf8065d9fe760640e5744896b764f9ebb6d2fa69
2013-04-10 15:16:46 +02:00
cffafa411c Makefile to build the arm bootloader
Change-Id: I865266c93bdab1c01d625a0ef50c4d9a0ccf7ba5
2013-03-21 15:44:06 +01:00
a7e5d2373f cmake/Bochs: Integrated Bochs configure into CMake
Bochs' configure options can now be set via ccmake.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2102 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-15 12:34:19 +00:00
ac3702b5e8 Rename: CONFIG_EVENT_RANGEBREAKPOINTS -> CONFIG_EVENT_BREAKPOINTS_RANGE
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2037 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-31 14:32:03 +00:00
db35166d67 - Added and updated documentation for gem5
- Added gem5 configuration used for profiling

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2027 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-30 23:59:32 +00:00
9c62e4a7f2 - Added signaling of trap situations needed in the weather-monitor to gem5.
- Fixed setting of instruction address for simulator.onMemoryAccess() calls.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2025 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-30 23:59:24 +00:00
03b4356598 Bugfix: Let Bochs' trigger breakpoint events even in case of rep-instructions
This reverts the solution of a former commit (see git hash e1f6601d8494bcb002e89543a9334e053f0e69d3). All additional changes proposed in that commit have been deleted and the major work is now done by the aspect header BreakRepeatInstr.ah: It ensures the condition in the methods repeat() and repeat_ZF() if (BX_CPU_THIS_PTR async_event) ... to be always true which causes Bochs to leave these methods immediately. This, in turn, involves a call to defineCPULoopJointPoint(), yielding a breakpoint event in Fail.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2009 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-17 13:41:19 +00:00
afca00ce0a - Added a define which marks the use of BPRangeListener
- Gem5 now has two different implementation for breakpoints.
  - If only BPSingleListener are used, gem5 Breakpoints are used
  - If BPRangeListener are used, gem5 calls onBreakpoint() in every simulated instruction

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2003 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-16 15:27:06 +00:00
b052c0494b Architecture changes (only gem5 implementation right now):
- The register manager is gone. It's functionality is now encapsulated in the
  CPU classes.
- For the client, there is the ConcreteCPU class that encapsulates the access
  to the CPU state (including registers) and architecture details. The
  correspondig objects for the CPUs inside the simulator can be accessed
  through the SimulatorController.getCPU() function.
- Listener got a new ConcreteCPU* member to filter for which CPU the events
  should fire. The default NULL is used as wildcard for all aviable CPUs. The
  events respectively got a ConcreteCPU* member to indicate which CPU really
  fired the event.
- For the server, there is CPUArchitecture to access the architecture details.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1966 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-02 17:50:46 +00:00
hsc
1f8dfd01e9 bochs: trace REP/REPZ/REPNZ iterations
This allows single-stepping through REP/REPZ/REPNZ iterations.  We mainly
need this for a little more realistic timing model when, e.g., copying
large memory areas with REP MOVSB.

Be aware that memory-access tracing only works reliably for REPxx-prefixed
instructions if Bochs was configured with --disable-repeat-speedups, as
this Bochs optimization completely circumvents the usual memory access
paths.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1885 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-11-06 15:43:24 +00:00
66fe662495 Gem5: functionalAccess() should not trigger memory access
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1862 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-28 23:50:06 +00:00
e0e95faa5b Restructured the gem5 backend:
- FailGem5Device is gone.
- There are now changes directly made to the gem5 source.
- Gem5Connector is a helper class that is compiled inside the gem5 context to workaround problems with gem5 header in fail.

Things that are working:
- BPSingleListener
- MemAccessListener
- Save and restore simulator state

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1820 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-24 19:19:14 +00:00
b41eec3f65 Adding gem5 source to svn.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1819 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-24 19:18:57 +00:00
hsc
773ad1367d uniform use of comments for Bochs modifications
We need to be able to grep for our manual changes.  It doesn't help to
have variations with "TUDOS" or "BOCHS-MODIFIED" around.  Please
understand "// DanceOS" comments as an abbreviation for "this code was
manually modified and needs to be manually ported once we switch to a
newer version of Bochs."

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1747 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-16 16:59:49 +00:00
fd102c01ea Important bugfix: passing the instruction cache entry pointer
does not account for arrays of instructions provided
by one virtual instruction trace cache entry ->
passing the current instruction directly.
ALUInstr not yet completely tested.


git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1704 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-01 17:51:34 +00:00
be9d2912f7 Correction - this _is_ necessary for instruction modification
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1702 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-27 19:50:31 +00:00
hsc
f9c96ddf2d prefix internal libraries to avoid naming conflicts with system libraries
This is a precaution to avoid current and future naming conflicts with
common system libraries.  libutil (part of libc) is the first, but probably
not the last example that already caused trouble twice.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1614 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-12 07:52:30 +00:00
f3f58750c9 Adding build description for gem5.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1460 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-07-29 16:11:14 +00:00
c06565aa4e Basic SAL files and makefile modifications for adding gem5.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1457 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-07-17 15:35:29 +00:00
hsc
765c5f6985 fix restore() in case no "natural" async_events occur
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1410 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-07-03 12:38:24 +00:00
hsc
83f64fd4bc removing build-system debug output
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1400 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-07-02 12:03:09 +00:00
hsc
4a4b3ea7e2 FailBochs build process reversed
The FailBochs client is not linked by the Bochs build system anymore, but
by our cmake scripts (make fail-client):
 -  All Bochs libraries are merged into libfailbochs.a (a new target
    within the Bochs Autotools scripts).
 -  The previous libfail.a is *not* a merge of all Fail* libraries anymore,
    but pulls these in via library dependencies.

Additionally I did a lot of build system cleanup, e.g. additional external
libraries may now be pulled in where they're needed.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1390 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-29 22:22:41 +00:00
bff60aeae3 Additionally passing the current Bochs CPU context and instruction cache entry to BochsController (enables detailed instruction analysis and modification)
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1361 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-15 16:39:14 +00:00
hsc
f74c794789 Bochs tweak: properly handle restore() after TimerEvent
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1331 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-12 15:13:15 +00:00
2575604b41 Fail* directories reorganized, Code-cleanup (-> coding-style), Typos+comments fixed.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-08 20:09:43 +00:00