Restructured the gem5 backend:

- FailGem5Device is gone.
- There are now changes directly made to the gem5 source.
- Gem5Connector is a helper class that is compiled inside the gem5 context to workaround problems with gem5 header in fail.

Things that are working:
- BPSingleListener
- MemAccessListener
- Save and restore simulator state

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1820 8c4709b5-6ec9-48aa-a5cd-a96041d1645a

simulators/gem5/src/base/hashmap.hh

@@ -76,6 +76,11 @@
 #endif
 #endif
 
+// FAIL*
+// don't use unordered map with aspect c++ compiler
+#undef HAVE_STD_UNORDERED_MAP
+#undef HAVE_STD_TR1_UNORDERED_MAP
+
 // set a default value of 0
 #ifndef HAVE_STD_UNORDERED_MAP
 #define HAVE_STD_UNORDERED_MAP 0

simulators/gem5/src/cpu/simple/base.cc

@@ -81,6 +81,9 @@
 #include "sim/stats.hh"
 #include "sim/system.hh"
 
+#include "sal/SALInst.hpp"
+#include "config/FailConfig.hpp"
+
 using namespace std;
 using namespace TheISA;
 
@@ -329,6 +332,10 @@ BaseSimpleCPU::checkForInterrupts()
         Fault interrupt = interrupts->getInterrupt(tc);
 
         if (interrupt != NoFault) {
+			// FAIL*
+			#ifdef CONFIG_EVENT_INTERRUPT
+			fail::simulator.onInterrupt(dynamic_cast<ArmFault*>(interrupt.get())->offset(), false);
+			#endif
             fetchOffset = 0;
             interrupts->updateIntrInfo(tc);
             interrupt->invoke(tc);

simulators/gem5/src/mem/abstract_mem.cc

@@ -62,6 +62,9 @@
 #include "mem/packet_access.hh"
 #include "sim/system.hh"
 
+#include "config/FailConfig.hpp"
+#include "sal/SALInst.hpp"
+
 using namespace std;
 
 AbstractMemory::AbstractMemory(const Params *p) :
@@ -400,6 +403,10 @@ AbstractMemory::access(PacketPtr pkt)
         bytesRead[pkt->req->masterId()] += pkt->getSize();
         if (pkt->req->isInstFetch())
             bytesInstRead[pkt->req->masterId()] += pkt->getSize();
+		// FAIL*
+		#ifdef CONFIG_EVENT_MEMREAD
+		fail::simulator.onMemoryAccess(pkt->getAddr(), pkt->getSize(), false, 0);
+		#endif
     } else if (pkt->isWrite()) {
         if (writeOK(pkt)) {
             if (pmemAddr)
@@ -408,6 +415,10 @@ AbstractMemory::access(PacketPtr pkt)
             TRACE_PACKET("Write");
             numWrites[pkt->req->masterId()]++;
             bytesWritten[pkt->req->masterId()] += pkt->getSize();
+			// FAIL*
+			#ifdef CONFIG_EVENT_MEMWRITE
+			fail::simulator.onMemoryAccess(pkt->getAddr(), pkt->getSize(), true, 0);
+			#endif
         }
     } else if (pkt->isInvalidate()) {
         // no need to do anything
@@ -432,11 +443,19 @@ AbstractMemory::functionalAccess(PacketPtr pkt)
         if (pmemAddr)
             memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
         TRACE_PACKET("Read");
+		// FAIL*
+		#ifdef CONFIG_EVENT_MEMREAD
+		fail::simulator.onMemoryAccess(pkt->getAddr(), pkt->getSize(), false, 0);
+		#endif
         pkt->makeResponse();
     } else if (pkt->isWrite()) {
         if (pmemAddr)
             memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize());
         TRACE_PACKET("Write");
+		// FAIL*
+		#ifdef CONFIG_EVENT_MEMWRITE
+		fail::simulator.onMemoryAccess(pkt->getAddr(), pkt->getSize(), true, 0);
+		#endif
         pkt->makeResponse();
     } else if (pkt->isPrint()) {
         Packet::PrintReqState *prs =

simulators/gem5/src/sim/root.cc

@@ -37,6 +37,8 @@
 #include "sim/full_system.hh"
 #include "sim/root.hh"
 
+#include "sal/SALInst.hpp"
+
 Root *Root::_root = NULL;
 
 /*
@@ -126,6 +128,14 @@ Root::loadState(Checkpoint *cp)
     timeSyncEnable(params()->time_sync_enable);
 }
 
+
+// FAIL*
+void
+Root::startup()
+{
+	fail::simulator.startup();
+}
+
 void
 Root::serialize(std::ostream &os)
 {

simulators/gem5/src/sim/root.hh

@@ -112,6 +112,9 @@ class Root : public SimObject
      */
     void initState();
 
+	// FAIL*
+	void startup();
+
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);