Architecture changes (only gem5 implementation right now):

- The register manager is gone. It's functionality is now encapsulated in the
  CPU classes.
- For the client, there is the ConcreteCPU class that encapsulates the access
  to the CPU state (including registers) and architecture details. The
  correspondig objects for the CPUs inside the simulator can be accessed
  through the SimulatorController.getCPU() function.
- Listener got a new ConcreteCPU* member to filter for which CPU the events
  should fire. The default NULL is used as wildcard for all aviable CPUs. The
  events respectively got a ConcreteCPU* member to indicate which CPU really
  fired the event.
- For the server, there is CPUArchitecture to access the architecture details.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1966 8c4709b5-6ec9-48aa-a5cd-a96041d1645a

simulators/gem5/src/cpu/simple/atomic.cc

@@ -57,6 +57,9 @@
 #include "sim/system.hh"
 #include "sim/full_system.hh"
 
+#include "config/FailConfig.hpp"
+#include "sal/SALInst.hpp"
+
 using namespace std;
 using namespace TheISA;
 
@@ -288,6 +291,12 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
 
             assert(!pkt.isError());
 
+			// FAIL*
+			#ifdef CONFIG_EVENT_MEMREAD
+			fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
+			fail::simulator.onMemoryAccess(cpu, pkt.getAddr(), pkt.getSize(), false, 0);
+			#endif
+
             if (req->isLLSC()) {
                 TheISA::handleLockedRead(thread, req);
             }
@@ -389,6 +398,12 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
                 dcache_access = true;
                 assert(!pkt.isError());
 
+				// FAIL*
+				#ifdef CONFIG_EVENT_MEMWRITE
+				fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
+				fail::simulator.onMemoryAccess(cpu, pkt.getAddr(), pkt.getSize(), true, 0);
+				#endif
+
                 if (req->isSwap()) {
                     assert(res);
                     memcpy(res, pkt.getPtr<uint8_t>(), fullSize);
@@ -482,6 +497,11 @@ AtomicSimpleCPU::tick()
                         icache_latency = icachePort.sendAtomic(&ifetch_pkt);
 
                     assert(!ifetch_pkt.isError());
+					// FAIL*
+					#ifdef CONFIG_EVENT_MEMREAD
+					fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
+					fail::simulator.onMemoryAccess(cpu, ifetch_pkt.getAddr(), ifetch_pkt.getSize(), false, 0);
+					#endif
 
                     // ifetch_req is initialized to read the instruction directly
                     // into the CPU object's inst field.

simulators/gem5/src/mem/abstract_mem.cc

@@ -403,10 +403,6 @@ AbstractMemory::access(PacketPtr pkt)
         bytesRead[pkt->req->masterId()] += pkt->getSize();
         if (pkt->req->isInstFetch())
             bytesInstRead[pkt->req->masterId()] += pkt->getSize();
-		// FAIL*
-		#ifdef CONFIG_EVENT_MEMREAD
-		fail::simulator.onMemoryAccess(pkt->getAddr(), pkt->getSize(), false, 0);
-		#endif
     } else if (pkt->isWrite()) {
         if (writeOK(pkt)) {
             if (pmemAddr)
@@ -415,10 +411,6 @@ AbstractMemory::access(PacketPtr pkt)
             TRACE_PACKET("Write");
             numWrites[pkt->req->masterId()]++;
             bytesWritten[pkt->req->masterId()] += pkt->getSize();
-			// FAIL*
-			#ifdef CONFIG_EVENT_MEMWRITE
-			fail::simulator.onMemoryAccess(pkt->getAddr(), pkt->getSize(), true, 0);
-			#endif
         }
     } else if (pkt->isInvalidate()) {
         // no need to do anything