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Revisited breakpoint implementation of gem5.

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Now, the gem5 implementation equals the Bochs variant. Note that its
necessary to enable CONFIG_EVENTS_BREAKPOINTS_RANGE in order to use
range breakpoints.
In addition, gem5 distinguishes between macro- and microops. With the
new implemenation, onBreakpoint is only called when a macroop changes.

Change-Id: Ib86d1802fc70c20d22ca1a1ece0e8d1221b2e7db
This commit is contained in:
Adrian Böckenkamp
2013-04-24 13:06:44 +02:00
parent f364024cba
commit a3cafbd78b
5 changed files with 8 additions and 81 deletions
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14
simulators/gem5/src/cpu/simple/base.cc
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@ -377,12 +377,6 @@ BaseSimpleCPU::preExecute()
TheISA::PCState pcState = thread->pcState();
// FAIL*
#if defined(CONFIG_EVENT_BREAKPOINTS) && defined(CONFIG_EVENT_BREAKPOINTS_RANGE)
fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
fail::simulator.onBreakpoint(cpu, instAddr(), -1);
#endif
if (isRomMicroPC(pcState.microPC())) {
stayAtPC = false;
curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(),
@ -406,6 +400,14 @@ BaseSimpleCPU::preExecute()
//Decode an instruction if one is ready. Otherwise, we'll have to
//fetch beyond the MachInst at the current pc.
instPtr = decoder->decode(pcState);
// FAIL*
#if defined(CONFIG_EVENT_BREAKPOINTS) || defined(CONFIG_EVENT_BREAKPOINTS_RANGE)
fail::ConcreteCPU* cpu = &fail::simulator.getCPU(cpuId());
fail::simulator.setMnemonic(instPtr->getName());
fail::simulator.onBreakpoint(cpu, instAddr(), -1);
#endif
if (instPtr) {
stayAtPC = false;
thread->pcState(pcState);