gem5 startup script: revisited fs.py to get rid of ARM linux images
In former versions, the aforementioned image was 'required' to run gem5 although it wasn't actually used at all. With the new python script fail_fs.py, it suffices to start gem5 on a target foo.elf by simply typing $ ../scripts/run-gem5.sh path/to/target/foo.elf Change-Id: I7f48460e50d48d55fe22f2381e2ae8aec8510233
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Adrian Böckenkamp
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simulators/gem5/configs/example/fail_fs.py
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185
simulators/gem5/configs/example/fail_fs.py
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# --------------------------------------------------------------
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# This script invokes the gem5 simulator. It is written to be used
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# with the Fail* framework. For further information, see
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# http://www.m5sim.org/Simulation_Scripts_Explained
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# This script is based on $FAIL/simulators/gem5/configs/example/fs.py
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#
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# Author: Adrian Böckenkamp
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#
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# --------------------------------------------------------------
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# Required Python modules:
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import optparse
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import sys
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import m5 # required by gem5
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from m5.objects import * # dito
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from m5.util import addToPath, fatal # some helpers
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addToPath('../common') # to find the next modules:
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from FSConfig import *
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import Simulation # for setWorkCountOptions(), run()
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import CacheConfig
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import Options # for parsing the command line
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# --------------------------------------------------------------
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# Configuration phase:
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parser = optparse.OptionParser() # TODO: functionality useful?
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Options.addCommonOptions(parser) # TODO: remove unused options
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Options.addFSOptions(parser) # TODO: dito
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(options, args) = parser.parse_args()
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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print "[Fail*] Welcome to the FULL SYSTEM simulation script for gem5!"
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# Sets up the low-level system parameter:
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class FailArmSystem(System):
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type = 'ArmSystem'
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load_addr_mask = 0xffffffff
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# 0x35 Implementor is '5' from "M5"
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# 0x0 Variant
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# 0xf Architecture from CPUID scheme
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# 0xc00 Primary part number ("c" or higher implies ARM v7)
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# 0x0 Revision
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midr_regval = Param.UInt32(0x350fc000, "MIDR value")
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multi_proc = Param.Bool(True, "Multiprocessor system?")
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boot_loader = Param.String("", "File that contains the boot loader code if any")
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gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface")
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flags_addr = Param.Addr(0, "Address of the flags register for MP booting")
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# Creates gem5-related (Python) system objects (hierarchy):
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def makeFailArmSystem(mem_mode, machine_type):
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assert machine_type
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self = FailArmSystem()
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# generic system
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mdesc = SysConfig()
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self.readfile = mdesc.script()
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self.iobus = NoncoherentBus()
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self.membus = MemBus()
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self.membus.badaddr_responder.warn_access = "warn"
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self.bridge = Bridge(delay='50ns', nack_delay='4ns')
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self.bridge.master = self.iobus.slave
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self.bridge.slave = self.membus.master
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self.mem_mode = mem_mode
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if machine_type == "RealView_PBX":
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self.realview = RealViewPBX()
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elif machine_type == "RealView_EB":
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self.realview = RealViewEB()
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elif machine_type == "VExpress_ELT":
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self.realview = VExpress_ELT()
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elif machine_type == "VExpress_EMM":
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self.realview = VExpress_EMM()
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self.load_addr_mask = 0xffffffff
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else:
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print "Unknown Machine Type"
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sys.exit(1)
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# No disk image / IDE controller interface stuff.
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# EOT character on UART will end the simulation
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self.realview.uart.end_on_eot = True
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self.physmem = SimpleMemory(range = AddrRange(Addr(mdesc.mem())),
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zero = True)
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self.physmem.port = self.membus.master
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self.realview.attachOnChipIO(self.membus, self.bridge)
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self.realview.attachIO(self.iobus)
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self.intrctrl = IntrControl()
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self.terminal = Terminal()
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self.vncserver = VncServer()
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self.system_port = self.membus.slave
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return self
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# Driver system CPU is always simple... note this is an assignment of
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# a class, not an instance.
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DriveCPUClass = AtomicSimpleCPU
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drive_mem_mode = 'atomic'
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# We use the atomic simple CPU model:
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class TestCPUClass(AtomicSimpleCPU): pass
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# "TestCPUClass" is our CPU class type (sic!), derived from AtomicSimpleCPU
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test_mem_mode = 'atomic'
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FutureClass = None
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TestCPUClass.clock = '2GHz'
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DriveCPUClass.clock = '2GHz'
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# Extract #CPUs:
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np = options.num_cpus
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# This script is only designed to be used with ARM targets. However,
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# it should be simple to extend it.
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if buildEnv['TARGET_ISA'] != "arm":
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fatal("Incapable of building %s full system (only for ARM)! You may want to try fs.py instead.", buildEnv['TARGET_ISA'])
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# Create the gem5 component hierarchy (see above for the definition).
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# In particular, it specifies system-specific parameters (e.g., Multi-
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# processor system flag, memory bus (type), an UART, ...):
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test_sys = makeFailArmSystem(test_mem_mode, options.machine_type)
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# Set the path to the kernel. Essentially, this the path to your
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# experiment target (e.g., the abo-simple-arm.elf file). It should
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# contain the bootload code as well.
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if options.kernel is not None:
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print "[Fail*] Using target: " + options.kernel
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test_sys.kernel = options.kernel
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else:
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print "[Fail*] No kernel target given, exiting!"
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sys.exit(1)
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test_sys.init_param = options.init_param
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# Construct the CPUs (np in total) and connect them to the "test system":
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test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
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# Create the memory:
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mem_size = SysConfig().mem()
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# Create the caches:
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if options.caches or options.l2cache:
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test_sys.iocache = IOCache(addr_ranges=[test_sys.physmem.range])
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test_sys.iocache.cpu_side = test_sys.iobus.master
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test_sys.iocache.mem_side = test_sys.membus.slave
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else:
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test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
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ranges = [test_sys.physmem.range])
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test_sys.iobridge.slave = test_sys.iobus.master
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test_sys.iobridge.master = test_sys.membus.slave
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# Sanity check
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if options.fastmem and (options.caches or options.l2cache):
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fatal("You cannot use fastmem in combination with caches!")
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for i in xrange(np):
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if options.fastmem:
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test_sys.cpu[i].fastmem = True
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if options.checker:
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test_sys.cpu[i].addCheckerCpu()
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CacheConfig.config_cache(options, test_sys)
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# Setup the root node and connect the hierarchy:
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root = Root(full_system=True, system=test_sys)
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# TODO: What's this for?
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if options.timesync:
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root.time_sync_enable = True
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# TODO: What's this for?
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if options.frame_capture:
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VncServer.frame_capture = True
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# --------------------------------------------------------------
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# Simulation phase:
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Simulation.setWorkCountOptions(test_sys, options) # see Simulation.py
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# In essence, "run(...)" calls m5.instantiate() and, finally, m5.simulate().
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Simulation.run(options, root, test_sys, FutureClass)
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