gem5: codebase patched to compile with ag++

This changes allows us to compile the gem5 simulator with ag++. It
was tested with ag++ v0.8, built Apr 18 2013. Most of the changes
are preprocessor directives like #ifndef __puma which have been
inserted into the gem5 code. Unfortunately, a python script and a
SWIG input file have been patched, too.
Additionally, the CMake file has been updated. A single call to
"make" now invokes the ag++ (instead of the g++) compiler front
end. The new CMake target "gem5-allclean" should be used to clean
the current project when building FailGem5. In addition to cleaning
the Fail build directory, it also invokes "scons -c" in the gem5
build directory; that is, gem5 is cleaned as well.

Change-Id: I20a92f025f34f626b81e30f2c873baeba189f83b

cmake/gem5.cmake

@@ -15,6 +15,10 @@ if(BUILD_GEM5)
   # - make gem5_build_config configurable in CMake
   #   (alternative: gem5_build_config is set based on the CMake build
   #    config, e.g., "Debug" or "Release")
+  # - Ideally, there is no additional "gem5-clean" target. Instead,
+  #   calling "make clean" should also invoke a clean command in the
+  #   gem5 root dir. This seems easy for "make only" projects--things
+  #   get shaky due to "scons".
 
   # Enable ExternalProject CMake module
   include(ExternalProject)
@@ -29,10 +33,15 @@ if(BUILD_GEM5)
     SOURCE_DIR ${gem5_src_dir}
     BINARY_DIR ${gem5_src_dir}
     # Build gem5 using scons build system:
-    BUILD_COMMAND scons EXTRAS=${gem5_wrapper} ${gem5_build_config} -j${core_count}
+    BUILD_COMMAND scons "CXX=${CMAKE_CXX_COMPILER} -p ${gem5_src_dir} --Xcompiler" EXTRAS=${gem5_wrapper} ${gem5_build_config} -j${core_count}
     # Disable install step (for now)
     INSTALL_COMMAND ""
   )
+  add_custom_target(gem5-allclean
+    COMMAND @echo "Cleaning Fail* and gem5 ..."
+    COMMAND cd "${PROJECT_BINARY_DIR}/" && make clean
+    COMMAND cd "${gem5_src_dir}/" && scons -c
+  )
 
   # Build "fail" library first (will be statically linked to gem5)
   add_dependencies(FailGem5_binary_external fail)

simulators/gem5/SConstruct

@@ -488,6 +488,9 @@ if main['GCC'] + main['SUNCC'] + main['ICC'] + main['CLANG'] > 1:
     print 'Error: How can we have two at the same time?'
     Exit(1)
 
+main['GCC'] = True
+main['GCC_VERSION'] = '4.4.5'
+
 # Set up default C++ compiler flags
 if main['GCC']:
     main.Append(CCFLAGS=['-pipe'])
@@ -496,14 +499,14 @@ if main['GCC']:
     # Read the GCC version to check for versions with bugs
     # Note CCVERSION doesn't work here because it is run with the CC
     # before we override it from the command line
-    gcc_version = readCommand([main['CXX'], '-dumpversion'], exception=False)
-    main['GCC_VERSION'] = gcc_version
-    if not compareVersions(gcc_version, '4.4.1') or \
-       not compareVersions(gcc_version, '4.4.2'):
-        print 'Info: Tree vectorizer in GCC 4.4.1 & 4.4.2 is buggy, disabling.'
-        main.Append(CCFLAGS=['-fno-tree-vectorize'])
-    if compareVersions(gcc_version, '4.6') >= 0:
-        main.Append(CXXFLAGS=['-std=c++0x'])
+#    gcc_version = readCommand([main['CXX'], '-dumpversion'], exception=False)
+#    main['GCC_VERSION'] = gcc_version
+#    if not compareVersions(gcc_version, '4.4.1') or \
+#       not compareVersions(gcc_version, '4.4.2'):
+#        print 'Info: Tree vectorizer in GCC 4.4.1 & 4.4.2 is buggy, disabling.'
+#        main.Append(CCFLAGS=['-fno-tree-vectorize'])
+#    if compareVersions(gcc_version, '4.6') >= 0:
+#        main.Append(CXXFLAGS=['-std=c++0x'])
 elif main['ICC']:
     pass #Fix me... add warning flags once we clean up icc warnings
 elif main['SUNCC']:

simulators/gem5/src/arch/isa_parser.py

@@ -582,12 +582,23 @@ class FloatRegOperand(Operand):
             func = 'setFloatRegOperandBits'
         if self.write_code != None:
             return self.buildWriteCode(func)
-        wb = '''
-        {
-            %s final_val = %s;
-            xc->%s(this, %d, final_val);\n
-            if (traceData) { traceData->setData(final_val); }
-        }''' % (self.ctype, self.base_name, func, self.dest_reg_idx)
+        # (DanceOS hack begin...
+        if self.ctype == 'int32_t' or self.ctype == 'int16_t':
+            print "Applying Fail* hack in %s@%s ... :-)" % \
+            (__file__, inspect.currentframe().f_lineno)
+            wb = '''
+            {
+                %s final_val = %s;
+                xc->%s(this, %d, final_val);\n
+                if (traceData) { traceData->setData((%s)final_val); }
+            }''' % (self.ctype, self.base_name, func, self.dest_reg_idx, "u%s" % self.ctype)
+        else: # ...DanceOS hack end)
+            wb = '''
+            {
+                %s final_val = %s;
+                xc->%s(this, %d, final_val);\n
+                if (traceData) { traceData->setData(final_val); }
+            }''' % (self.ctype, self.base_name, func, self.dest_reg_idx)
         return wb
 
 class ControlRegOperand(Operand):

simulators/gem5/src/base/debug.cc

@@ -101,14 +101,18 @@ void
 CompoundFlag::enable()
 {
     SimpleFlag::enable();
+#ifndef __puma // DanceOS (error: no matching function for call to `mem_fun')
     for_each(_kids.begin(), _kids.end(), mem_fun(&Flag::enable));
+#endif
 }
 
 void
 CompoundFlag::disable()
 {
     SimpleFlag::disable();
+#ifndef __puma // DanceOS (error: no matching function for call to `mem_fun')
     for_each(_kids.begin(), _kids.end(), mem_fun(&Flag::disable));
+#endif    
 }
 
 struct AllFlags : public Flag

simulators/gem5/src/base/inet.cc

@@ -102,7 +102,10 @@ string
 EthAddr::string() const
 {
     stringstream stream;
+// DanceOS modification
+#ifndef __puma
     stream << *this;
+#endif
     return stream.str();
 }
 

simulators/gem5/src/base/random.hh

@@ -69,6 +69,7 @@ class Random
         value = genrand() & (int8_t)-1;
     }
 
+#ifndef __puma // DanceOS (redefinition of `_random')
     void
     _random(int16_t &value)
     {
@@ -86,6 +87,7 @@ class Random
     {
         value = (int64_t)genrand() << 32 | (int64_t)genrand();
     }
+#endif // DanceOS
 
     void
     _random(uint8_t &value)
@@ -136,6 +138,7 @@ class Random
         return static_cast<int8_t>(min + genrand(diff));
     }
 
+#ifndef __puma // DanceOS (redefinition of `_random')
     int16_t
     _random(int16_t min, int16_t max)
     {
@@ -156,6 +159,7 @@ class Random
         uint64_t diff = max - min;
         return static_cast<int64_t>(min + genrand(diff));
     }
+#endif // DanceOS
 
     uint8_t
     _random(uint8_t min, uint8_t max)

simulators/gem5/src/base/time.hh

@@ -264,7 +264,10 @@ operator-(const Time &l, const Time &r)
 inline std::ostream &
 operator<<(std::ostream &out, const Time &time)
 {
+	// DanceOS modification
+#ifndef __puma
     out << time.date();
+#endif
     return out;
 }
 

simulators/gem5/src/cpu/o3/commit_impl.hh

@@ -355,6 +355,8 @@ DefaultCommit<Impl>::setROB(ROB *rob_ptr)
     rob = rob_ptr;
 }
 
+#ifndef __puma // DanceOS (left operand of `->' not pointer to class object)
+
 template <class Impl>
 void
 DefaultCommit<Impl>::initStage()
@@ -1342,6 +1344,8 @@ DefaultCommit<Impl>::markCompletedInsts()
     }
 }
 
+#endif // !__puma (DanceOS)
+
 template <class Impl>
 bool
 DefaultCommit<Impl>::robDoneSquashing()

simulators/gem5/src/cpu/o3/decode_impl.hh

@@ -214,6 +214,8 @@ DefaultDecode<Impl>::checkStall(ThreadID tid) const
     return ret_val;
 }
 
+#ifndef __puma // DanceOS (left operand of `->' not pointer to class object)
+
 template<class Impl>
 inline bool
 DefaultDecode<Impl>::fetchInstsValid()
@@ -759,3 +761,5 @@ DefaultDecode<Impl>::decodeInsts(ThreadID tid)
         wroteToTimeBuffer = true;
     }
 }
+
+#endif // !__puma (DanceOS)

simulators/gem5/src/cpu/o3/fetch_impl.hh

@@ -826,6 +826,8 @@ DefaultFetch<Impl>::squash(const TheISA::PCState &newPC,
     cpu->removeInstsNotInROB(tid);
 }
 
+#ifndef __puma // DanceOS (left operand of `->' not pointer to class object)
+
 template <class Impl>
 void
 DefaultFetch<Impl>::tick()
@@ -1514,6 +1516,8 @@ DefaultFetch<Impl>::lsqCount()
     return InvalidThreadID;
 }
 
+#endif // !__puma (DanceOS)
+
 template<class Impl>
 ThreadID
 DefaultFetch<Impl>::branchCount()

simulators/gem5/src/cpu/o3/iew_impl.hh

@@ -281,6 +281,8 @@ DefaultIEW<Impl>::regStats()
     wbRate = writebackCount / cpu->numCycles;
 }
 
+#ifndef __puma // DanceOS (left operand of `->' not pointer to class object)
+
 template<class Impl>
 void
 DefaultIEW<Impl>::initStage()
@@ -1668,3 +1670,5 @@ DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
         }
     }
 }
+
+#endif // !__puma (DanceOS)

simulators/gem5/src/cpu/o3/inst_queue_impl.hh

@@ -1116,6 +1116,8 @@ InstructionQueue<Impl>::violation(DynInstPtr &store,
     memDepUnit[store->threadNumber].violation(store, faulting_load);
 }
 
+#ifndef __puma // DanceOS (left operand of `->' not pointer to class object)
+
 template <class Impl>
 void
 InstructionQueue<Impl>::squash(ThreadID tid)
@@ -1136,6 +1138,8 @@ InstructionQueue<Impl>::squash(ThreadID tid)
     memDepUnit[tid].squash(squashedSeqNum[tid], tid);
 }
 
+#endif // !__puma (DanceOS)
+
 template <class Impl>
 void
 InstructionQueue<Impl>::doSquash(ThreadID tid)

simulators/gem5/src/cpu/o3/rename_impl.hh

@@ -335,6 +335,8 @@ DefaultRename<Impl>::takeOverFrom()
     }
 }
 
+#ifndef __puma // DanceOS (left operand of `->' not pointer to class object)
+
 template <class Impl>
 void
 DefaultRename<Impl>::squash(const InstSeqNum &squash_seq_num, ThreadID tid)
@@ -1338,6 +1340,8 @@ DefaultRename<Impl>::checkSignalsAndUpdate(ThreadID tid)
     return false;
 }
 
+#endif // !__puma (DanceOS)
+
 template<class Impl>
 void
 DefaultRename<Impl>::serializeAfter(InstQueue &inst_list, ThreadID tid)

simulators/gem5/src/mem/ruby/network/orion/ConfigFile.cc

@@ -41,8 +41,9 @@ ConfigFile::ConfigFile( string filename, string delimiter,
     std::ifstream in( filename.c_str() );
 
     if( !in ) throw file_not_found( filename ); 
-
+#ifndef __puma
     in >> (*this);
+#endif
 }
 
 

simulators/gem5/src/mem/ruby/network/orion/OrionConfig.hh

@@ -103,7 +103,9 @@ T OrionConfig::get(const string& key_) const
     it = m_params_map.find(key_);
     if (it == m_params_map.end()) 
     {
+#ifndef __puma // error: invalid operand to binary `<<'
         std::cerr << key_ << " NOT FOUND!" << std::endl;
+#endif
         throw key_not_found(key_);
     }
     return string_as_T<T>(it->second);
@@ -138,8 +140,10 @@ inline bool OrionConfig::string_as_T<bool>(const string& str_)
     }
     else
     {
+#ifndef __puma
         std::cerr << "Invalid bool value: '" << str_ <<
           "'. Treated as FALSE." << std::endl;
+#endif
         ret = false;
     }
     return ret;

simulators/gem5/src/python/swig/core.i

@@ -58,7 +58,9 @@ inline void disableAllListeners() { ListenSocket::disableAll(); }
 inline void
 seedRandom(uint64_t seed)
 {
+#ifndef __puma // DanceOS
     random_mt.init(seed);
+#endif
 }
 
 %}

simulators/gem5/src/sim/insttracer.hh

@@ -114,9 +114,12 @@ class InstRecord
     void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
     void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
 
+// DanceOS modification
+#ifndef __puma // bug #375
     void setData(int64_t d) { setData((uint64_t)d); }
     void setData(int32_t d) { setData((uint32_t)d); }
     void setData(int16_t d) { setData((uint16_t)d); }
+#endif
     void setData(int8_t d)  { setData((uint8_t)d); }
 
     void setData(double d) { data.as_double = d; data_status = DataDouble; }

simulators/gem5/src/sim/process.cc

@@ -198,7 +198,9 @@ Process::openInputFile(const string &filename)
 
     if (fd == -1) {
         perror(NULL);
+#ifndef __puma // DanceOS (invalid operand to binary `<<')
         cerr << "unable to open \"" << filename << "\" for reading\n";
+#endif
         fatal("can't open input file");
     }
 
@@ -213,7 +215,9 @@ Process::openOutputFile(const string &filename)
 
     if (fd == -1) {
         perror(NULL);
+#ifndef __puma // DanceOS (invalid operand to binary `<<')
         cerr << "unable to open \"" << filename << "\" for writing\n";
+#endif
         fatal("can't open output file");
     }
 

simulators/gem5/src/sim/syscall_emul.cc

@@ -796,7 +796,8 @@ cloneFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
         ctc->clearArchRegs();
 
         // Arch-specific cloning code
-        #if THE_ISA == ALPHA_ISA or THE_ISA == X86_ISA
+//      #if THE_ISA == ALPHA_ISA or THE_ISA == X86_ISA
+        #if THE_ISA == ALPHA_ISA || THE_ISA == X86_ISA // DanceOS: "or" replaced with "||"
             // Cloning the misc. regs for these archs is enough
             TheISA::copyMiscRegs(tc, ctc);
         #elif THE_ISA == SPARC_ISA

simulators/gem5/src/sim/syscall_emul.hh

@@ -934,6 +934,7 @@ fstatfsFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
         return -EBADF;
 
     struct statfs hostBuf;
+    int fstatfs(int fd, struct statfs *buf); // DanceOS (added forward decl.)
     int result = fstatfs(fd, &hostBuf);
 
     if (result < 0)

simulators/gem5/src/sim/vptr.hh

@@ -72,7 +72,9 @@ class VPtr
             return;
 
         FSTranslatingPortProxy &proxy = tc->getVirtProxy();
+#ifndef __puma // DanceOS (no matching function for call to `readBlob')
         proxy.readBlob(ptr, buffer, sizeof(T));
+#endif
     }
 
     bool