c8a9039f36
#error msg for gem5 + x85 added (not supported yet)
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2082 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-14 14:45:13 +00:00
fdb39c9613
correction of commit 2079
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2080 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-13 13:16:18 +00:00
a2830fa140
JobClient: weighting for throughput calculation
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The new troughput is now calculated as:
0.5*old throughput + 0.5* the current throughput of the last job-set.
This prevents excessive variations in the calculation of the new
throughput.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2079 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-13 13:11:29 +00:00
7f587d461c
ArmArchitecture::fillRegisterList(): set textual register name appropriately
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For some reasons, the compiler cannot find a matching Register::setName(const std::string&) although it is implemented in sal/Register.cc. The work around fixes this issue.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2077 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-07 14:17:49 +00:00
0303f00d72
ElfReader::getSectionSize(): return type of definition should equal the return type of the declaration (i.e., guest_address_t)
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This caused a compilation error on ARM (+gem5).
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2076 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-07 11:54:27 +00:00
f96f4dd360
typo-fix
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2075 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-07 10:43:07 +00:00
609ac58c8f
ElfReader now supports section information.
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ElfReader can now get Section start address,
end address and size by its name.
Or the according section name to any address within
a section
See ElfReader.hpp for API.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2070 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-07 00:51:25 +00:00
3307987895
Added missing virtual Destructor, fixes gcc warning
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2068 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-07 00:51:19 +00:00
94214063ac
Fixed whitespaces.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2067 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-07 00:51:14 +00:00
d9808c0fca
DEBUG flag in BochsController not needed anymore
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It is a remnant of former times. ;-)
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2065 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-06 15:39:54 +00:00
5c4b132550
~SimulatorController: do not free ConcreteCPU object ptr in the base class
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In fact, delete should be called in the destructor of each derived class (BochsController and Gem5Controller at the moment).
Additionally, this is the reason why ~SimulatorController is declared as virtual.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2064 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-06 15:39:50 +00:00
552a5fb4ac
coding-style++, comments++, FIXMEs++
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2063 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-06 15:39:46 +00:00
38b7064189
Make CPUArchitecure::addRegister protected: no need to modify the register config in an experiment
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2062 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-06 15:39:41 +00:00
8ce25257c3
bugfix: compile with libstdc++-4.7
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2049 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-01 13:57:42 +00:00
179272abea
Once an experiment terminates, all results will be sent to the server.
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One an experiment terminates, sending the results back to the server will
be initiated by the jobclients destructor.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2042 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-31 16:33:43 +00:00
542ee51c4b
Method to query the number of undone jobs in JocClient.hpp added.
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Since several jobs can be fetched from the server, it is interesting to
know how much undone jobs are still available. This will accomplished by
the new method getNumberOfUndoneJobs().
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2041 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-31 16:33:39 +00:00
e98b18e678
Breakpoint aspects updated
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The aspects respond to the new CONFIG_EVENT_BREAKPOINT_RANGE flag now.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2040 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-31 14:32:14 +00:00
ac3702b5e8
Rename: CONFIG_EVENT_RANGEBREAKPOINTS -> CONFIG_EVENT_BREAKPOINTS_RANGE
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2037 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-31 14:32:03 +00:00
582c8617d3
CPUArchitecture: iterator added to allow iterating over all registers
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2036 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-31 12:19:02 +00:00
cb429fddb2
typos fixed.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2032 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-31 12:18:47 +00:00
db35166d67
- Added and updated documentation for gem5
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- Added gem5 configuration used for profiling
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2027 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-30 23:59:32 +00:00
58c5ef98f4
typo-fix: ExperimentData.hpp
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2020 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-24 13:26:22 +00:00
ff2dc189ce
Correction of commit 2014
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2019 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-24 11:26:26 +00:00
bcb48344ea
revert "bugfix: typo in CMakeLists.txt (CLIENT_JOB_LIMIT -> CLIENT_JOB_LIMIT_SEC)"
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This reverts commit 270d37e929e584786fc40a336a9f73962182648f.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2018 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-24 11:21:16 +00:00
ed3e81d290
bugfix: typo in CMakeLists.txt (CLIENT_JOB_LIMIT -> CLIENT_JOB_LIMIT_SEC)
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2017 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-24 11:05:33 +00:00
00f809231f
Code cleanup for commit 1963-1965
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2014 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-23 14:22:05 +00:00
125914a305
BochsRegister.hpp and BochsRegisterIDs.hpp not needed anymore
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The includes of these headers have already been removed from the experiments. In the current code, the content of the header BochsRegister.hpp is rather simply copied to x86/Architecture.hpp. It is therefore necessary to revisit the code soon (especially the FIXME related to register IDs).
Another problem is that there is no generalization of register IDs. Thus, all experiments are currently specific to a concrete architecture (which is not desired).
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2010 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-17 13:41:23 +00:00
03b4356598
Bugfix: Let Bochs' trigger breakpoint events even in case of rep-instructions
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This reverts the solution of a former commit (see git hash e1f6601d8494bcb002e89543a9334e053f0e69d3). All additional changes proposed in that commit have been deleted and the major work is now done by the aspect header BreakRepeatInstr.ah: It ensures the condition in the methods repeat() and repeat_ZF() if (BX_CPU_THIS_PTR async_event) ... to be always true which causes Bochs to leave these methods immediately. This, in turn, involves a call to defineCPULoopJointPoint(), yielding a breakpoint event in Fail.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2009 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-17 13:41:19 +00:00
0ba62aea8f
Both performance aspects need to respect the argument order of their target methods (pointcuts)
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Additionaly, the CPU object is passed to the Event object construction in ordner to set the trigger CPU ptr (in PerfVector{Watchpoints,Breakpoints}::gather()) properly.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2008 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-17 13:41:15 +00:00
edf44aec28
Bugfixes for aspect headers due to architecure-related changes.
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Now, each aspect calls it's corresponding event headler by providing the new CPU object pointer as well.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2007 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-17 13:41:11 +00:00
214bb36b47
onIOPort needs to have a ConcreteCPU argument as well; detectCPU() added
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detectCPU() allows us to easily retrieve the current Fail-CPU object which is a regular use case in the aspect headers, now. (Another solution would be a slice in the Bochs CPU class which inserts a reference to the Fail CPU object. Maybe we 'll implement this at a later point.)
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2006 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-17 13:41:07 +00:00
d3cf2359a4
FIXMEs and comments updated due to last architecture-related changes
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2005 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-17 13:41:03 +00:00
c4e5ab4f58
Fixed reading of instruction pointer for gem5.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2004 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-16 15:27:10 +00:00
afca00ce0a
- Added a define which marks the use of BPRangeListener
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- Gem5 now has two different implementation for breakpoints.
- If only BPSingleListener are used, gem5 Breakpoints are used
- If BPRangeListener are used, gem5 calls onBreakpoint() in every simulated instruction
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2003 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-16 15:27:06 +00:00
ac7cec7684
ElfReader: Constructor tries to get ELF from ENV FAIL_ELF_PATH
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2002 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-15 12:53:49 +00:00
0972a22bc9
Warn and show hint, if libiberty (needed by demangler) not found
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1996 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-11 16:39:03 +00:00
4051c0f4e9
ElfReader: Added support for de/mangled symbols
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See vezs-example experiment for usage.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1985 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-21 12:12:25 +00:00
5a3a66da25
Reverse search getNameByAddress.
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Implemented with the help of boost bimap.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1983 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-20 22:06:46 +00:00
f8aa1237e9
Make FailBochs compile again (after changes in r1966).
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For now, only breakpoints are working. Other event sources need to be revised, too.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1981 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:43 +00:00
2010d4c385
Created default x86 CPU interface classes.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1980 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:39 +00:00
d019f64bf5
Export Bochs 64 bit ability (if enabled).
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This is required to add the architecture-dependent registers.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1979 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:35 +00:00
bc0da74104
ArmArchitecture: improve destructor speed by calling clear() instead of erase().
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1978 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:32 +00:00
692172a164
ArmArchitecture: set ARM register names (textual ddescription) as well.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1977 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:28 +00:00
d3ccc75269
ArmCPUState: no need to repeat abstract method declarations
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(...if they have already been defined in the base class).
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1976 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:24 +00:00
9f53d3348b
SimulatorController: no need for return type bool of addCPU().
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1975 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:21 +00:00
25f75b299c
coding style fixed, some FIXMEs and comments added.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1974 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:17 +00:00
0799d5dcf1
Fixed include name
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1971 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-06 21:22:51 +00:00
2b36678737
Separated Architecture and CPUState classes for ARM/Gem5 (*Architecture will be used in the campaign).
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1969 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-05 13:05:24 +00:00
b981fdcfea
coding style++
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1968 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-05 12:40:34 +00:00
35753cd075
coding style++, some TODOs added.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1967 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-05 12:27:17 +00:00
