9 Commits
Author SHA1 Message Date
christoph 441a303fd3 Update env 2025-06-30 22:49:19 +02:00
christoph 111ff0c8d0 Reassemble programs 2023-03-30 16:34:19 +02:00
christoph 3ebced585f Start at ROM address 1 2023-03-30 16:34:14 +02:00
christoph 01d1d4b632 Reassemble programs 2023-03-29 19:24:28 +02:00
christoph 95d911c3be Fix an output format bug 2023-03-29 19:24:21 +02:00
christoph f554efcd7d Reassemble example programs 2023-03-29 19:14:00 +02:00
christoph a7f4bf6e92 Update format to SystemVerilog Module 2023-03-29 19:13:51 +02:00
christoph 28a7c14059 Update .gitignore 2023-03-29 19:13:41 +02:00
christoph 8114c9b5fd Initial commit (from Logisim-Assembler) 2023-03-29 18:47:37 +02:00