christoph/systemverilog-rom-assembler
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Reassemble programs

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This commit is contained in:
Christoph Urlacher
2023-03-30 16:34:19 +02:00
parent 3ebced585f
commit 111ff0c8d0
4 changed files with 41 additions and 41 deletions
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22
programs/add_and_jump.sv
View File

@ -6,17 +6,17 @@ module ROM(
);
always @(address) case (address)
8'b00000000: dataout = 8'b00000101;
8'b00000001: dataout = 8'b10000001;
8'b00000010: dataout = 8'b00001010;
8'b00000011: dataout = 8'b10000010;
8'b00000100: dataout = 8'b01000100;
8'b00000101: dataout = 8'b10011001;
8'b00000110: dataout = 8'b00001111;
8'b00000111: dataout = 8'b10000010;
8'b00001000: dataout = 8'b01000101;
8'b00001001: dataout = 8'b00000000;
8'b00001010: dataout = 8'b11000001;
8'b00000001: dataout = 8'b00000101;
8'b00000010: dataout = 8'b10000001;
8'b00000011: dataout = 8'b00001010;
8'b00000100: dataout = 8'b10000010;
8'b00000101: dataout = 8'b01000100;
8'b00000110: dataout = 8'b10011001;
8'b00000111: dataout = 8'b00001111;
8'b00001000: dataout = 8'b10000010;
8'b00001001: dataout = 8'b01000101;
8'b00001010: dataout = 8'b00000000;
8'b00001011: dataout = 8'b11000001;
default: dataout = 8'b00000000;
endcase

44
programs/counting.sv
View File

@ -6,28 +6,28 @@ module ROM(
);
always @(address) case (address)
8'b00000000: dataout = 8'b00110000;
8'b00000001: dataout = 8'b10000110;
8'b00000010: dataout = 8'b00110001;
8'b00000011: dataout = 8'b10000110;
8'b00000100: dataout = 8'b00110010;
8'b00000101: dataout = 8'b10000110;
8'b00000110: dataout = 8'b00110011;
8'b00000111: dataout = 8'b10000110;
8'b00001000: dataout = 8'b00110100;
8'b00001001: dataout = 8'b10000110;
8'b00001010: dataout = 8'b00110101;
8'b00001011: dataout = 8'b10000110;
8'b00001100: dataout = 8'b00110110;
8'b00001101: dataout = 8'b10000110;
8'b00001110: dataout = 8'b00110111;
8'b00001111: dataout = 8'b10000110;
8'b00010000: dataout = 8'b00111000;
8'b00010001: dataout = 8'b10000110;
8'b00010010: dataout = 8'b00111001;
8'b00010011: dataout = 8'b10000110;
8'b00010100: dataout = 8'b00000000;
8'b00010101: dataout = 8'b11000100;
8'b00000001: dataout = 8'b00110000;
8'b00000010: dataout = 8'b10000110;
8'b00000011: dataout = 8'b00110001;
8'b00000100: dataout = 8'b10000110;
8'b00000101: dataout = 8'b00110010;
8'b00000110: dataout = 8'b10000110;
8'b00000111: dataout = 8'b00110011;
8'b00001000: dataout = 8'b10000110;
8'b00001001: dataout = 8'b00110100;
8'b00001010: dataout = 8'b10000110;
8'b00001011: dataout = 8'b00110101;
8'b00001100: dataout = 8'b10000110;
8'b00001101: dataout = 8'b00110110;
8'b00001110: dataout = 8'b10000110;
8'b00001111: dataout = 8'b00110111;
8'b00010000: dataout = 8'b10000110;
8'b00010001: dataout = 8'b00111000;
8'b00010010: dataout = 8'b10000110;
8'b00010011: dataout = 8'b00111001;
8'b00010100: dataout = 8'b10000110;
8'b00010101: dataout = 8'b00000000;
8'b00010110: dataout = 8'b11000100;
default: dataout = 8'b00000000;
endcase

10
programs/input_output.sv
View File

@ -6,11 +6,11 @@ module ROM(
);
always @(address) case (address)
8'b00000000: dataout = 8'b10110001;
8'b00000001: dataout = 8'b00001010;
8'b00000010: dataout = 8'b10000010;
8'b00000011: dataout = 8'b01000100;
8'b00000100: dataout = 8'b10011110;
8'b00000001: dataout = 8'b10110001;
8'b00000010: dataout = 8'b00001010;
8'b00000011: dataout = 8'b10000010;
8'b00000100: dataout = 8'b01000100;
8'b00000101: dataout = 8'b10011110;
default: dataout = 8'b00000000;
endcase

6
programs/nop_and_jump.sv
View File

@ -6,9 +6,9 @@ module ROM(
);
always @(address) case (address)
8'b00000000: dataout = 8'b11000000;
8'b00000001: dataout = 8'b00000000;
8'b00000010: dataout = 8'b11000100;
8'b00000001: dataout = 8'b11000000;
8'b00000010: dataout = 8'b00000000;
8'b00000011: dataout = 8'b11000100;
default: dataout = 8'b00000000;
endcase