christoph/systemverilog-rom-assembler
1
Fork 0
Code Activity

Reassemble example programs

Browse Source
This commit is contained in:
Christoph Urlacher
2023-03-29 19:14:00 +02:00
parent a7f4bf6e92
commit f554efcd7d
12 changed files with 89 additions and 68 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
programs/add_and_jump.cpu8_v1
View File

@ -1,17 +0,0 @@
v3.0 hex words addressed
00: 05 81 0a 82 44 99 0f 82 45 00 c1 00 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

23
programs/add_and_jump.sv Normal file
View File

@ -0,0 +1,23 @@
`default_nettype none
module ROM(
input var logic[7:0] address,
output var logic[7:0] dataout
);
always @(address) case (address)
case 8'b00000000: dataout = 8'b00000101;
case 8'b00000001: dataout = 8'b10000001;
case 8'b00000010: dataout = 8'b00001010;
case 8'b00000011: dataout = 8'b10000010;
case 8'b00000100: dataout = 8'b01000100;
case 8'b00000101: dataout = 8'b10011001;
case 8'b00000110: dataout = 8'b00001111;
case 8'b00000111: dataout = 8'b10000010;
case 8'b00001000: dataout = 8'b01000101;
case 8'b00001001: dataout = 8'b00000000;
case 8'b00001010: dataout = 8'b11000001;
default: dataout = 8'b00000000;
endcase
endmodule

0
programs/add_and_jump.lasm8_v1 → programs/add_and_jump.svrasm
View File

17
programs/counting.cpu8_v1
View File

@ -1,17 +0,0 @@
v3.0 hex words addressed
00: 30 86 31 86 32 86 33 86 34 86 35 86 36 86 37 86
10: 38 86 39 86 00 c4 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

34
programs/counting.sv Normal file
View File

@ -0,0 +1,34 @@
`default_nettype none
module ROM(
input var logic[7:0] address,
output var logic[7:0] dataout
);
always @(address) case (address)
case 8'b00000000: dataout = 8'b00110000;
case 8'b00000001: dataout = 8'b10000110;
case 8'b00000010: dataout = 8'b00110001;
case 8'b00000011: dataout = 8'b10000110;
case 8'b00000100: dataout = 8'b00110010;
case 8'b00000101: dataout = 8'b10000110;
case 8'b00000110: dataout = 8'b00110011;
case 8'b00000111: dataout = 8'b10000110;
case 8'b00001000: dataout = 8'b00110100;
case 8'b00001001: dataout = 8'b10000110;
case 8'b00001010: dataout = 8'b00110101;
case 8'b00001011: dataout = 8'b10000110;
case 8'b00001100: dataout = 8'b00110110;
case 8'b00001101: dataout = 8'b10000110;
case 8'b00001110: dataout = 8'b00110111;
case 8'b00001111: dataout = 8'b10000110;
case 8'b00010000: dataout = 8'b00111000;
case 8'b00010001: dataout = 8'b10000110;
case 8'b00010010: dataout = 8'b00111001;
case 8'b00010011: dataout = 8'b10000110;
case 8'b00010100: dataout = 8'b00000000;
case 8'b00010101: dataout = 8'b11000100;
default: dataout = 8'b00000000;
endcase
endmodule

0
programs/counting.lasm8_v1 → programs/counting.svrasm
View File

17
programs/input_output.cpu8_v1
View File

@ -1,17 +0,0 @@
v3.0 hex words addressed
00: b1 0a 82 44 9e 00 00 00 00 00 00 00 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

17
programs/input_output.sv Normal file
View File

@ -0,0 +1,17 @@
`default_nettype none
module ROM(
input var logic[7:0] address,
output var logic[7:0] dataout
);
always @(address) case (address)
case 8'b00000000: dataout = 8'b10110001;
case 8'b00000001: dataout = 8'b00001010;
case 8'b00000010: dataout = 8'b10000010;
case 8'b00000011: dataout = 8'b01000100;
case 8'b00000100: dataout = 8'b10011110;
default: dataout = 8'b00000000;
endcase
endmodule

0
programs/input_output.lasm8_v1 → programs/input_output.svrasm
View File

17
programs/nop_and_jump.cpu8_v1
View File

@ -1,17 +0,0 @@
v3.0 hex words addressed
00: c0 00 c4 00 00 00 00 00 00 00 00 00 00 00 00 00
10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

15
programs/nop_and_jump.sv Normal file
View File

@ -0,0 +1,15 @@
`default_nettype none
module ROM(
input var logic[7:0] address,
output var logic[7:0] dataout
);
always @(address) case (address)
case 8'b00000000: dataout = 8'b11000000;
case 8'b00000001: dataout = 8'b00000000;
case 8'b00000010: dataout = 8'b11000100;
default: dataout = 8'b00000000;
endcase
endmodule

0
programs/nop_and_jump.lasm8_v1 → programs/nop_and_jump.svrasm
View File