24 lines
690 B
Systemverilog
24 lines
690 B
Systemverilog
`default_nettype none
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module ROM(
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input var logic[7:0] address,
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output var logic[7:0] dataout
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);
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always @(address) case (address)
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case 8'b00000000: dataout = 8'b00000101;
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case 8'b00000001: dataout = 8'b10000001;
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case 8'b00000010: dataout = 8'b00001010;
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case 8'b00000011: dataout = 8'b10000010;
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case 8'b00000100: dataout = 8'b01000100;
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case 8'b00000101: dataout = 8'b10011001;
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case 8'b00000110: dataout = 8'b00001111;
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case 8'b00000111: dataout = 8'b10000010;
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case 8'b00001000: dataout = 8'b01000101;
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case 8'b00001001: dataout = 8'b00000000;
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case 8'b00001010: dataout = 8'b11000001;
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default: dataout = 8'b00000000;
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endcase
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endmodule
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