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dc4f25dc89
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Remove the clock inputs from ALU and Cond again (for now)
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2023-03-30 16:27:56 +02:00 |
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5b0d12183d
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Remove unnecessary default case from ConditionalUnit
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2023-03-30 13:22:45 +02:00 |
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f472994fda
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Add clock input to ALU/ConditionalUnit
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2023-03-30 00:21:47 +02:00 |
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ea5b2c53c2
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Add missing "signed" to ALU ports/connections
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2023-03-29 15:03:20 +02:00 |
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49d1871dfa
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Implement ALU/Register components
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2023-03-23 21:51:50 +01:00 |
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