32 lines
831 B
Systemverilog
32 lines
831 B
Systemverilog
`default_nettype none
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// Inst: MD OP
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// 11 000 XXX
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// OPs: 000 - Never
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// 001 - == 0
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// 010 - < 0
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// 011 - <= 0
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// 100 - Always
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// 101 - != 0
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// 110 - > 0
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// 111 - >= 0
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module ConditionalUnit(
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input var logic[2:0] opcode,
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input var logic signed[7:0] operand,
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output var logic result
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);
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// This could be simplified significantly (basically removed), if I had ALU flags.
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always_comb case (opcode)
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3'b000: result = 0;
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3'b001: result = (operand == 0);
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3'b010: result = (operand < 0);
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3'b011: result = (operand <= 0);
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3'b100: result = 1;
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3'b101: result = (operand != 0);
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3'b110: result = (operand > 0);
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3'b111: result = (operand >= 0);
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default: result = 0;
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endcase
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endmodule
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