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201 Commits
Author SHA1 Message Date
hoffmann 39a6415001 T32: Integrated Register read/write calls 
* Tested without connected Lauterbach.
  T32_* functions are mocked via aspect.

* New target t32cli, for sending T32 command cia cli. (for testing)

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2103 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-15 18:06:02 +00:00
adrian bf9e111b9f no need for a separate fillRegisterList() method(only called once) 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2086 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-14 14:45:30 +00:00
adrian e81517645f doc for X86CPUState added, FIXME removed 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2085 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-14 14:45:26 +00:00
adrian 3cc40e62c7 A few CPUState-related methods should be const (getter) 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2084 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-14 14:45:22 +00:00
adrian accfba8237 coding-style++, gem5 code doc added 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2083 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-14 14:45:18 +00:00
adrian c8a9039f36 #error msg for gem5 + x85 added (not supported yet) 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2082 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-14 14:45:13 +00:00
hellwig fdb39c9613 correction of commit 2079 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2080 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-13 13:16:18 +00:00
hellwig a2830fa140 JobClient: weighting for throughput calculation 
The new troughput is now calculated as:
0.5*old throughput + 0.5* the current throughput of the last job-set.

This prevents excessive variations in the calculation of the new
throughput.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2079 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-13 13:11:29 +00:00
adrian 7f587d461c ArmArchitecture::fillRegisterList(): set textual register name appropriately 
For some reasons, the compiler cannot find a matching Register::setName(const std::string&) although it is implemented in sal/Register.cc. The work around fixes this issue.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2077 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-07 14:17:49 +00:00
adrian 0303f00d72 ElfReader::getSectionSize(): return type of definition should equal the return type of the declaration (i.e., guest_address_t) 
This caused a compilation error on ARM (+gem5).

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2076 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-07 11:54:27 +00:00
adrian f96f4dd360 typo-fix 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2075 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-07 10:43:07 +00:00
hoffmann 609ac58c8f ElfReader now supports section information. 
ElfReader can now get Section start address,
end address and size by its name.
Or the according section name to any address within
a section

See ElfReader.hpp for API.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2070 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-07 00:51:25 +00:00
hoffmann 3307987895 Added missing virtual Destructor, fixes gcc warning 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2068 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-07 00:51:19 +00:00
hoffmann 94214063ac Fixed whitespaces. 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2067 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-07 00:51:14 +00:00
adrian d9808c0fca DEBUG flag in BochsController not needed anymore 
It is a remnant of former times. ;-)

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2065 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-06 15:39:54 +00:00
adrian 5c4b132550 ~SimulatorController: do not free ConcreteCPU object ptr in the base class 
In fact, delete should be called in the destructor of each derived class (BochsController and Gem5Controller at the moment).

Additionally, this is the reason why ~SimulatorController is declared as virtual.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2064 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-06 15:39:50 +00:00
adrian 552a5fb4ac coding-style++, comments++, FIXMEs++ 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2063 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-06 15:39:46 +00:00
adrian 38b7064189 Make CPUArchitecure::addRegister protected: no need to modify the register config in an experiment 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2062 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-06 15:39:41 +00:00
hsc 8ce25257c3 bugfix: compile with libstdc++-4.7 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2049 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-02-01 13:57:42 +00:00
hellwig 179272abea Once an experiment terminates, all results will be sent to the server. 
One an experiment terminates, sending the results back to the server will
be initiated by the jobclients destructor.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2042 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-31 16:33:43 +00:00
hellwig 542ee51c4b Method to query the number of undone jobs in JocClient.hpp added. 
Since several jobs can be fetched from the server, it is interesting to
know how much undone jobs are still available. This will accomplished by
the new method getNumberOfUndoneJobs().

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2041 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-31 16:33:39 +00:00
hellwig e98b18e678 Breakpoint aspects updated 
The aspects respond to the new CONFIG_EVENT_BREAKPOINT_RANGE flag now.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2040 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-31 14:32:14 +00:00
hellwig ac3702b5e8 Rename: CONFIG_EVENT_RANGEBREAKPOINTS -> CONFIG_EVENT_BREAKPOINTS_RANGE 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2037 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-31 14:32:03 +00:00
adrian 582c8617d3 CPUArchitecture: iterator added to allow iterating over all registers 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2036 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-31 12:19:02 +00:00
adrian cb429fddb2 typos fixed. 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2032 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-31 12:18:47 +00:00
friemel db35166d67 - Added and updated documentation for gem5 
- Added gem5 configuration used for profiling

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2027 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-30 23:59:32 +00:00
adrian 58c5ef98f4 typo-fix: ExperimentData.hpp 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2020 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-24 13:26:22 +00:00
hellwig ff2dc189ce Correction of commit 2014 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2019 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-24 11:26:26 +00:00
adrian bcb48344ea revert "bugfix: typo in CMakeLists.txt (CLIENT_JOB_LIMIT -> CLIENT_JOB_LIMIT_SEC)" 
This reverts commit 270d37e929e584786fc40a336a9f73962182648f.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2018 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-24 11:21:16 +00:00
adrian ed3e81d290 bugfix: typo in CMakeLists.txt (CLIENT_JOB_LIMIT -> CLIENT_JOB_LIMIT_SEC) 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2017 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-24 11:05:33 +00:00
hellwig 00f809231f Code cleanup for commit 1963-1965 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2014 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-23 14:22:05 +00:00
adrian 125914a305 BochsRegister.hpp and BochsRegisterIDs.hpp not needed anymore 
The includes of these headers have already been removed from the experiments. In the current code, the content of the header BochsRegister.hpp is rather simply copied to x86/Architecture.hpp. It is therefore necessary to revisit the code soon (especially the FIXME related to register IDs).

Another problem is that there is no generalization of register IDs. Thus, all experiments are currently specific to a concrete architecture (which is not desired).

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2010 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-17 13:41:23 +00:00
adrian 03b4356598 Bugfix: Let Bochs' trigger breakpoint events even in case of rep-instructions 
This reverts the solution of a former commit (see git hash e1f6601d8494bcb002e89543a9334e053f0e69d3). All additional changes proposed in that commit have been deleted and the major work is now done by the aspect header BreakRepeatInstr.ah: It ensures the condition in the methods repeat() and repeat_ZF() if (BX_CPU_THIS_PTR async_event) ... to be always true which causes Bochs to leave these methods immediately. This, in turn, involves a call to defineCPULoopJointPoint(), yielding a breakpoint event in Fail.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2009 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-17 13:41:19 +00:00
adrian 0ba62aea8f Both performance aspects need to respect the argument order of their target methods (pointcuts) 
Additionaly, the CPU object is passed to the Event object construction in ordner to set the trigger CPU ptr (in PerfVector{Watchpoints,Breakpoints}::gather()) properly.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2008 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-17 13:41:15 +00:00
adrian edf44aec28 Bugfixes for aspect headers due to architecure-related changes. 
Now, each aspect calls it's corresponding event headler by providing the new CPU object pointer as well.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2007 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-17 13:41:11 +00:00
adrian 214bb36b47 onIOPort needs to have a ConcreteCPU argument as well; detectCPU() added 
detectCPU() allows us to easily retrieve the current Fail-CPU object which is a regular use case in the aspect headers, now. (Another solution would be a slice in the Bochs CPU class which inserts a reference to the Fail CPU object. Maybe we 'll implement this at a later point.)

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2006 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-17 13:41:07 +00:00
adrian d3cf2359a4 FIXMEs and comments updated due to last architecture-related changes 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2005 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-17 13:41:03 +00:00
friemel c4e5ab4f58 Fixed reading of instruction pointer for gem5. 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2004 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-16 15:27:10 +00:00
friemel afca00ce0a - Added a define which marks the use of BPRangeListener 
- Gem5 now has two different implementation for breakpoints.
  - If only BPSingleListener are used, gem5 Breakpoints are used
  - If BPRangeListener are used, gem5 calls onBreakpoint() in every simulated instruction

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2003 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-16 15:27:06 +00:00
hoffmann ac7cec7684 ElfReader: Constructor tries to get ELF from ENV FAIL_ELF_PATH 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2002 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-15 12:53:49 +00:00
hoffmann 0972a22bc9 Warn and show hint, if libiberty (needed by demangler) not found 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1996 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2013-01-11 16:39:03 +00:00
hoffmann 4051c0f4e9 ElfReader: Added support for de/mangled symbols 
See vezs-example experiment for usage.



git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1985 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2012-12-21 12:12:25 +00:00
hoffmann 5a3a66da25 Reverse search getNameByAddress. 
Implemented with the help of boost bimap.



git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1983 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2012-12-20 22:06:46 +00:00
adrian f8aa1237e9 Make FailBochs compile again (after changes in r1966). 
For now, only breakpoints are working. Other event sources need to be revised, too.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1981 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2012-12-12 13:08:43 +00:00
adrian 2010d4c385 Created default x86 CPU interface classes. 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1980 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2012-12-12 13:08:39 +00:00
adrian d019f64bf5 Export Bochs 64 bit ability (if enabled). 
This is required to add the architecture-dependent registers.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1979 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2012-12-12 13:08:35 +00:00
adrian bc0da74104 ArmArchitecture: improve destructor speed by calling clear() instead of erase(). 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1978 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2012-12-12 13:08:32 +00:00
adrian 692172a164 ArmArchitecture: set ARM register names (textual ddescription) as well. 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1977 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2012-12-12 13:08:28 +00:00
adrian d3ccc75269 ArmCPUState: no need to repeat abstract method declarations 
(...if they have already been defined in the base class).

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1976 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2012-12-12 13:08:24 +00:00
adrian 9f53d3348b SimulatorController: no need for return type bool of addCPU(). 
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1975 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
 2012-12-12 13:08:21 +00:00