a328a21887
Renamed x86- and ARM-specific source files (for improved readability).
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Updated include paths and CMake config appropriately
Change-Id: Ida5045cde0458b3031e64b73853fe5f58ef5a9d6
2013-04-03 16:46:51 +02:00
ff2aec5d7e
T32SIM: evaluating mem access via trace correctly :)
2013-03-21 18:58:04 +01:00
b8e706b1a5
T32SIM: Integrating Tracing feature of the T32SIM.
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After each simulator break, T32Tracer retrieves the latest (16)
trace records from the T32. Memory address and value can now
be evaluated easily from the trace record.
TODO:Nevertheless we still have to traverse the trace to
find the instruction causing the access.
2013-03-21 18:57:46 +01:00
f586351e79
T32: Dissassembler to evaluate memory instructions.
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For the T32 variant we have to evaluate the memory
access instruction to find out, which memory address
was accessed.
Dissassmbly by OpenOCDs arm_disassembler.hpp/.cc:
- fine for ARM / Thumb1
- needs fixes for Thumb2 :( (currently doing that..)
2013-03-11 12:17:53 +01:00
bf9e111b9f
no need for a separate fillRegisterList() method(only called once)
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2086 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-14 14:45:30 +00:00
3cc40e62c7
A few CPUState-related methods should be const (getter)
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2084 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-14 14:45:22 +00:00
accfba8237
coding-style++, gem5 code doc added
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2083 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-14 14:45:18 +00:00
7f587d461c
ArmArchitecture::fillRegisterList(): set textual register name appropriately
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For some reasons, the compiler cannot find a matching Register::setName(const std::string&) although it is implemented in sal/Register.cc. The work around fixes this issue.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2077 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-07 14:17:49 +00:00
552a5fb4ac
coding-style++, comments++, FIXMEs++
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2063 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-06 15:39:46 +00:00
38b7064189
Make CPUArchitecure::addRegister protected: no need to modify the register config in an experiment
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2062 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-06 15:39:41 +00:00
c4e5ab4f58
Fixed reading of instruction pointer for gem5.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2004 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-16 15:27:10 +00:00
bc0da74104
ArmArchitecture: improve destructor speed by calling clear() instead of erase().
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1978 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:32 +00:00
692172a164
ArmArchitecture: set ARM register names (textual ddescription) as well.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1977 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:28 +00:00
d3ccc75269
ArmCPUState: no need to repeat abstract method declarations
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(...if they have already been defined in the base class).
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1976 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:24 +00:00
25f75b299c
coding style fixed, some FIXMEs and comments added.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1974 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:17 +00:00
0799d5dcf1
Fixed include name
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1971 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-06 21:22:51 +00:00
2b36678737
Separated Architecture and CPUState classes for ARM/Gem5 (*Architecture will be used in the campaign).
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1969 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-05 13:05:24 +00:00
35753cd075
coding style++, some TODOs added.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1967 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-05 12:27:17 +00:00
b052c0494b
Architecture changes (only gem5 implementation right now):
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- The register manager is gone. It's functionality is now encapsulated in the
CPU classes.
- For the client, there is the ConcreteCPU class that encapsulates the access
to the CPU state (including registers) and architecture details. The
correspondig objects for the CPUs inside the simulator can be accessed
through the SimulatorController.getCPU() function.
- Listener got a new ConcreteCPU* member to filter for which CPU the events
should fire. The default NULL is used as wildcard for all aviable CPUs. The
events respectively got a ConcreteCPU* member to indicate which CPU really
fired the event.
- For the server, there is CPUArchitecture to access the architecture details.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1966 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-02 17:50:46 +00:00
