christoph/quartus-8-bit-cpu
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Update Quartus project files

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This commit is contained in:
Christoph Urlacher
2023-03-29 15:59:23 +02:00
parent 6366984b50
commit 0ba622d9c0
3 changed files with 22 additions and 7 deletions
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27
CPU.qsf
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@ -39,7 +39,7 @@
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CGXFC5C6F27C7
set_global_assignment -name TOP_LEVEL_ENTITY LogicalUnit_TestBench
set_global_assignment -name TOP_LEVEL_ENTITY RegisterFile_TestBench
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:27:08 MäRZ 23, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
@ -65,9 +65,8 @@ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name SYSTEMVERILOG_FILE ALU_TestBench.sv
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH LogicalUnit_TestBench -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH RegisterFile_TestBench -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME ALU_TestBench -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ALU_TestBench
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ALU_TestBench -section_id ALU_TestBench
@ -76,13 +75,29 @@ set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 10000
set_global_assignment -name BOARD "Cyclone V GX Starter Kit"
set_global_assignment -name EDA_TEST_BENCH_NAME LogicalUnit_TestBench -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id LogicalUnit_TestBench
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME LogicalUnit_TestBench -section_id LogicalUnit_TestBench
set_global_assignment -name SYSTEMVERILOG_FILE LogicalUnit_TestBench.sv
set_global_assignment -name SYSTEMVERILOG_FILE ArithmeticUnit_TestBench.sv
set_global_assignment -name EDA_TEST_BENCH_NAME ArithmeticUnit_TestBench -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ArithmeticUnit_TestBench
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ArithmeticUnit_TestBench -section_id ArithmeticUnit_TestBench
set_global_assignment -name SYSTEMVERILOG_FILE ALU_TestBench.sv
set_global_assignment -name SYSTEMVERILOG_FILE ConditionalUnit_TestBench.sv
set_global_assignment -name EDA_TEST_BENCH_NAME ConditionalUnit_TestBench -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ConditionalUnit_TestBench
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ConditionalUnit_TestBench -section_id ConditionalUnit_TestBench
set_global_assignment -name SYSTEMVERILOG_FILE RegisterFile_TestBench.sv
set_global_assignment -name EDA_TEST_BENCH_NAME RegisterFile_TestBench -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id RegisterFile_TestBench
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME RegisterFile_TestBench -section_id RegisterFile_TestBench
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name EDA_TEST_BENCH_FILE ALU_TestBench.sv -section_id ALU_TestBench
set_global_assignment -name EDA_TEST_BENCH_NAME LogicalUnit_TestBench -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id LogicalUnit_TestBench
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME LogicalUnit_TestBench -section_id LogicalUnit_TestBench
set_global_assignment -name EDA_TEST_BENCH_FILE LogicalUnit_TestBench.sv -section_id LogicalUnit_TestBench
set_global_assignment -name EDA_TEST_BENCH_FILE ArithmeticUnit_TestBench.sv -section_id ArithmeticUnit_TestBench
set_global_assignment -name EDA_TEST_BENCH_FILE ConditionalUnit_TestBench.sv -section_id ConditionalUnit_TestBench
set_global_assignment -name EDA_TEST_BENCH_FILE RegisterFile_TestBench.sv -section_id RegisterFile_TestBench
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top