diff --git a/CPU.qsf b/CPU.qsf index c295d6b..d951bea 100644 --- a/CPU.qsf +++ b/CPU.qsf @@ -39,7 +39,7 @@ set_global_assignment -name FAMILY "Cyclone V" set_global_assignment -name DEVICE 5CGXFC5C6F27C7 -set_global_assignment -name TOP_LEVEL_ENTITY LogicalUnit_TestBench +set_global_assignment -name TOP_LEVEL_ENTITY RegisterFile_TestBench set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:27:08 MäRZ 23, 2023" set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" @@ -65,9 +65,8 @@ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF -set_global_assignment -name SYSTEMVERILOG_FILE ALU_TestBench.sv set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation -set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH LogicalUnit_TestBench -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH RegisterFile_TestBench -section_id eda_simulation set_global_assignment -name EDA_TEST_BENCH_NAME ALU_TestBench -section_id eda_simulation set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ALU_TestBench set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ALU_TestBench -section_id ALU_TestBench @@ -76,13 +75,29 @@ set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 10000 set_global_assignment -name BOARD "Cyclone V GX Starter Kit" +set_global_assignment -name EDA_TEST_BENCH_NAME LogicalUnit_TestBench -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id LogicalUnit_TestBench +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME LogicalUnit_TestBench -section_id LogicalUnit_TestBench set_global_assignment -name SYSTEMVERILOG_FILE LogicalUnit_TestBench.sv +set_global_assignment -name SYSTEMVERILOG_FILE ArithmeticUnit_TestBench.sv +set_global_assignment -name EDA_TEST_BENCH_NAME ArithmeticUnit_TestBench -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ArithmeticUnit_TestBench +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ArithmeticUnit_TestBench -section_id ArithmeticUnit_TestBench +set_global_assignment -name SYSTEMVERILOG_FILE ALU_TestBench.sv +set_global_assignment -name SYSTEMVERILOG_FILE ConditionalUnit_TestBench.sv +set_global_assignment -name EDA_TEST_BENCH_NAME ConditionalUnit_TestBench -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ConditionalUnit_TestBench +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ConditionalUnit_TestBench -section_id ConditionalUnit_TestBench +set_global_assignment -name SYSTEMVERILOG_FILE RegisterFile_TestBench.sv +set_global_assignment -name EDA_TEST_BENCH_NAME RegisterFile_TestBench -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id RegisterFile_TestBench +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME RegisterFile_TestBench -section_id RegisterFile_TestBench set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name EDA_TEST_BENCH_FILE ALU_TestBench.sv -section_id ALU_TestBench -set_global_assignment -name EDA_TEST_BENCH_NAME LogicalUnit_TestBench -section_id eda_simulation -set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id LogicalUnit_TestBench -set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME LogicalUnit_TestBench -section_id LogicalUnit_TestBench set_global_assignment -name EDA_TEST_BENCH_FILE LogicalUnit_TestBench.sv -section_id LogicalUnit_TestBench +set_global_assignment -name EDA_TEST_BENCH_FILE ArithmeticUnit_TestBench.sv -section_id ArithmeticUnit_TestBench +set_global_assignment -name EDA_TEST_BENCH_FILE ConditionalUnit_TestBench.sv -section_id ConditionalUnit_TestBench +set_global_assignment -name EDA_TEST_BENCH_FILE RegisterFile_TestBench.sv -section_id RegisterFile_TestBench set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/CPU.qws b/CPU.qws deleted file mode 100644 index ba8e725..0000000 Binary files a/CPU.qws and /dev/null differ diff --git a/CPU_nativelink_simulation.rpt b/CPU_nativelink_simulation.rpt index 930f4f4..ddc5eb5 100644 --- a/CPU_nativelink_simulation.rpt +++ b/CPU_nativelink_simulation.rpt @@ -18,6 +18,6 @@ Sim dir : simulation/modelsim Info: Starting NativeLink simulation with ModelSim-Altera software Sourced NativeLink script /nix/store/l9gl96q63whg0j0nknh5mspr9gxqprf4-quartus-prime-lite-unwrapped-20.1.1.720/quartus/common/tcl/internal/nativelink/modelsim.tcl -Warning: File CPU_run_msim_rtl_verilog.do already exists - backing up current file as CPU_run_msim_rtl_verilog.do.bak10 +Warning: File CPU_run_msim_rtl_verilog.do already exists - backing up current file as CPU_run_msim_rtl_verilog.do.bak11 Info: Spawning ModelSim-Altera Simulation software Info: NativeLink simulation flow was successful