d019f64bf5
Export Bochs 64 bit ability (if enabled).
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This is required to add the architecture-dependent registers.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1979 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:35 +00:00
25f75b299c
coding style fixed, some FIXMEs and comments added.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1974 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:17 +00:00
5135c79c05
TimerListener: microsecond granularity (ms is too coarse)
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1952 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-11-23 15:35:08 +00:00
9c3755363b
bochs bugfix: store the timer ID for correct deregistration
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Over a few indirections, this broke Bochs' 16550 UART simulation after
transferring a few hundreds of bytes. The UART uses internal timers to
simulate the configured baud rate; these timers cease to work after
repeated misuse from the Fail/Bochs bridge.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1887 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-11-06 18:29:45 +00:00
1668e21ce1
bochs: removed preprocessor nonsense
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It doesn't make sense to let timer (de)registration depend on
CONFIG_EVENT_BREAKPOINTS.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1886 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-11-06 18:29:41 +00:00
0b8710872b
Removed BochController debug stuff. Merged: BochsController::onBreakpoint -> SimCon::onBreakpoint.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1883 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-11-06 11:40:05 +00:00
0d1618746c
sal/bochs: move register IDs to a separate file
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This is necessary as a temporary fix: Currently, campaign code cannot use
Fail*'s architecture abstractions at all (e.g., we cannot iterate over all
existing GP registers). Until this is corrected by separating a concrete
backend and architecture information (the latter being usable by a
campaign), we now at least can use register IDs.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1792 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-22 15:36:09 +00:00
a911ebb353
Revert "explicit aspect activation"
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Unfortunately, this does not (yet) work as advertised. I need to fight another
round of CMake battles before retrying. Reverting to previous state for now.
This reverts r1753.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1767 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-19 09:45:00 +00:00
a29ad39f5e
explicit aspect activation
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ag++ is now called with a list of currently active aspect headers
(ag++ -a aspect1.ah -a aspect2.ah ...). This resolves several problems at
once:
- Build directories may be positioned arbitrarily now, they need not be
a subdirectory of the project anymore.
- Multiple build directories can coexist within the project tree. Before
this commit, the generated instantiate-*.ah aspect headers disturbed
neighboring build trees.
- Due to this, the regression test should be runnable much more easily
now.
- The build time was reduced by an average of about 10%.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1753 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-17 15:22:23 +00:00
6100472e1b
redundant include
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1746 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-16 16:59:46 +00:00
171d178309
SimCon interface update: save returns a boolean, now (+ redundant virtual keywords removed).
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1724 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-05 12:12:56 +00:00
42a75fa128
Documentation / corrected Bochs timer
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1718 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-05 09:41:41 +00:00
0c3d365368
bugfix: Add BochsListener to CMakeLists, workaround for onTimerTrigger
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1717 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-04 15:38:56 +00:00
2b79e83d72
Make it comile again with CONFIG_FAST_BREAKPOINTS enabled (avoid include cycle, see r1706), set timer id correctly (setId), coding-style + comment fix.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1712 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-04 11:20:31 +00:00
7d49b6f063
Simulator specific listener are now implemented using aspects instead of an additional inheritance level
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1706 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-02 11:42:18 +00:00
fd102c01ea
Important bugfix: passing the instruction cache entry pointer
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does not account for arrays of instructions provided
by one virtual instruction trace cache entry ->
passing the current instruction directly.
ALUInstr not yet completely tested.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1704 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-01 17:51:34 +00:00
00b16ae5d0
(Fail)Bochs bug documented in more detail: TimerListener cannot be added at boot time.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1697 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-27 09:32:32 +00:00
057c216dc0
Removed BufferCache stuff (fast breakpoints will do the job, see r1685).
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1686 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-25 11:36:19 +00:00
0cb6b39490
Aspect-based implementation of fast breakpoints added (optional).
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1685 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-25 10:10:02 +00:00
4e321409b7
several FIXMEs on virtual BaseListener functions
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1638 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-13 20:08:39 +00:00
f913d3f1ac
disabling debug output
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1623 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-12 16:10:38 +00:00
f795bf63c4
qemu: IOPortListener
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1622 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-12 16:05:18 +00:00
d40113c535
qemu: MemWriteListener specialization
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1619 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-12 14:07:15 +00:00
8cadb3e5c6
bochs: version not hardcoded anymore
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1617 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-12 14:07:10 +00:00
2fed94ae49
global interrupt_to_fire seems not to be Bochs-specific at the moment
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FIXME: This shouldn't be a global variable (probably a SimulatorController
member?). Reconsider interrupt generation being part of the generic
interface.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1612 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-11 17:10:11 +00:00
4f18dd945e
MemoryController: guestToHost should not be part of the abstract iface
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Not all backends have their memory mapped to a Fail*-accessible address.
Especially hardware targets can only be accessed indirectly.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1611 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-11 17:10:08 +00:00
e24099d4a8
Bochs aspects: check for BUILD_BOCHS everywhere
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1610 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-11 17:10:04 +00:00
10d0344505
typos
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1609 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-11 17:10:00 +00:00
402ca4ec45
Added mechanism to specialize listener + basic BPSingleListener for gem5
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1603 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-07 00:57:05 +00:00
8ca5893b69
bugfix: config header missing in save/restore/BP aspects
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1602 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-06 18:14:19 +00:00
9588a30f5b
Interface unification: BochsController implements onBreakpoint() instead of onInstrPtrChanged().
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1510 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-08-27 12:09:45 +00:00
a22ab1744c
bugfix: Bochs reboot results in invalid CPU state
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Bochs' CPU loop hook is not the right place to trigger a reboot; the EIP
increment soon thereafter leaves the CPU in an invalid state:
00194392696e[CPU0 ] prefetch: EIP [00010000] > CS.limit [0000ffff]
00194392698e[CPU0 ] prefetch: EIP [00010000] > CS.limit [0000ffff]
00194392700e[CPU0 ] prefetch: EIP [00010000] > CS.limit [0000ffff]
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Instead, do it where the "reboot" button also does it -- synchronously in a
timer handler.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1507 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-08-27 11:30:06 +00:00
ca17c793e7
Fail* now builds with hsc-simple as experiment for gem5.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1503 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-08-22 14:20:26 +00:00
9a23dbbb42
comments and coding-style fixed.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1498 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-08-16 14:26:11 +00:00
adb2bf2787
Comments + Coding-Style fixed.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1461 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-07-30 13:34:52 +00:00
ef45841b91
MemAccess aspect: only save rmw_address if MEMREAD/MEMWRITE is enabled
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1456 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-07-16 18:21:09 +00:00
e4570d95bd
Bochs aspects -> BochsController interface renamings
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SimulatorController::on...Listener() does not really make sense: These
functions are called when a specific event occurs in the simulator. A
"Listener" cannot occur. Renaming these to "on..." for now; we could
alternatively use "on...Event" later.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1455 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-07-16 18:21:06 +00:00
a78911702a
Events -> Listeners, waitAny -> resume, addEventAndWait -> addListenerAndResume, ... (refactoring), updated experiments/plugin accordingly, coding-style fixed.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1448 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-07-12 10:37:54 +00:00
13d5e4dbeb
Bochs-modifying aspect: never abort/ask the user on what to do
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1428 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-07-05 16:31:14 +00:00
ababa48fd7
reboot (and interrupt injection?) are also async_events
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1411 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-07-03 13:26:58 +00:00
765c5f6985
fix restore() in case no "natural" async_events occur
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1410 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-07-03 12:38:24 +00:00
fe915e7d52
++coding-style.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1388 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-27 11:27:06 +00:00
ac5dee6549
Renamed EventList -> EventManager (refactoring).
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1387 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-27 11:15:42 +00:00
58822b02f3
Some improvements on L4, and correcting a mistake made in revision 1361 (see mailing list).
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1377 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-21 14:19:21 +00:00
d143d6ae50
EvendId -> event_id_t (refactoring).
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1370 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-21 11:18:38 +00:00
ad0cfb9b11
Pre-/postprocessing is done within the event objects (Bochs-specific event added), ++coding-style.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1366 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-21 10:47:22 +00:00
bff60aeae3
Additionally passing the current Bochs CPU context and instruction cache entry to BochsController (enables detailed instruction analysis and modification)
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1361 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-15 16:39:14 +00:00
f49fa07a25
Changed BufferCache Backend to STL (as proposed), added IOPortEvent-Cache, updated class diagram
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1325 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-10 19:32:05 +00:00
13cd951a87
Bugfix in BufferCache, added some security checks, plus minor stuff in doc/howtobuild.txt
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1323 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-09 17:31:32 +00:00
2575604b41
Fail* directories reorganized, Code-cleanup (-> coding-style), Typos+comments fixed.
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git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1321 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-06-08 20:09:43 +00:00
