Add clock input to ALU/ConditionalUnit
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3
ALU.sv
3
ALU.sv
@ -9,6 +9,7 @@
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// 100 - ADD
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// 101 - SUB
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module ALU(
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input var logic clock,
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input var logic[2:0] opcode,
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input var logic signed[7:0] operandA,
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input var logic signed[7:0] operandB,
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@ -37,7 +38,7 @@ module ALU(
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// "always @(opcode or operandA or operandB)"
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// This didn't work though, the result didn't update correctly.
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// TODO: Figure out why
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always @(lu_result or au_result) case (opcode)
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always @(posedge clock) case (opcode)
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3'b000,
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3'b001,
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3'b010,
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