From f472994fda4f74b48b4b2c63597bbc1a0d68ff48 Mon Sep 17 00:00:00 2001
From: ChUrl <christoph.urlacher@protonmail.com>
Date: Thu, 30 Mar 2023 00:21:47 +0200
Subject: [PATCH] Add clock input to ALU/ConditionalUnit

---
 ALU.sv             | 3 ++-
 ConditionalUnit.sv | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/ALU.sv b/ALU.sv
index a531212..dc1dfc3 100644
--- a/ALU.sv
+++ b/ALU.sv
@@ -9,6 +9,7 @@
 //              100 - ADD
 //              101 - SUB
 module ALU(
+  input var logic clock,
   input var logic[2:0] opcode,
   input var logic signed[7:0] operandA,
   input var logic signed[7:0] operandB,
@@ -37,7 +38,7 @@ module ALU(
   // "always @(opcode or operandA or operandB)"
   // This didn't work though, the result didn't update correctly.
   // TODO: Figure out why
-  always @(lu_result or au_result) case (opcode)
+  always @(posedge clock) case (opcode)
     3'b000,
     3'b001,
     3'b010,
diff --git a/ConditionalUnit.sv b/ConditionalUnit.sv
index d241fca..501ed71 100644
--- a/ConditionalUnit.sv
+++ b/ConditionalUnit.sv
@@ -11,13 +11,14 @@
 //              110 - >  0
 //              111 - >= 0
 module ConditionalUnit(
+  input var logic clock,
   input var logic[2:0] opcode,
   input var logic signed[7:0] operand,
   output var logic result
 );
 
   // This could be simplified significantly (basically removed), if I had ALU flags.
-  always_comb case (opcode)
+  always @(posedge clock) case (opcode)
     3'b000: result = 0;
     3'b001: result = (operand == 0);
     3'b010: result = (operand < 0);