The output format of the tracing plugin needs to be as follows:
For a position in execution, first the PC-Event needs to be sent up
to the simulator controller, afterwards potential MEM-Events can be
signaled.
This order requirement is fixed with this commit.
Change-Id: I8412dd7a5a85a58c50a0d0d9b9d0369c838bc0a3
As memory writes have high fix costs, we want to minimize the number
of writes in consequence of the mmu configuration.
This commit aggregates writes as far as possible.
Change-Id: I4ba6618fc9023ae4a353585710e2933d3d7a6051
Decoding the current instruction sometimes failes, so we need
to extract the currently activated watchpoint from the openocd
internal list of watchpoints. If we have more than one watchpoint,
we are in trouble.
Change-Id: I14b172e4f933ca894cf66685c6d2ca8e573a3151
On ARM we need to add a offset to the pc, if we read it
(ARM ARM (DDI 0100I) page A2-9). This fixes bugs in memory
trace generation and watchpoint recognition.
Change-Id: I1cfcb84af2abae7971869d2ce29d602648e2f020
If we halt in a watchpoint, we need to figure out, which one it was.
This will from now on be done by decoding the current instruction.
Change-Id: Ib62df0016c60044f2618af00e853b4373eb00bd7
As we want to use the cortex-m3 only for memory access, it should
always be halted. To achieve this, we need to halt it after every
reboot.
Change-Id: I5f0edf4986b65aea5a2aa59020247b9676de4dcb
Halting can now be done for cortex-a9 and cortex-m3 target with the halting
function which originally was only able to halt the cortex-a9 target.
Change-Id: I9ced64253405654c4155c8f776534bc7231387b2
As the cycle counter seems to be running forth, we need to halt it, to
get exact cycle count values.
Change-Id: Id85c052b88cec48b25ee0975ad47369587e08096
Single-stepping as in tracing sometimes fails in a long step-chain.
So we repeat the step until it really stepped. It can be observed, that
if openocd returns a step error, it never accidently steps nonetheless.
To ensure this behaviour, we could check for correct pc.
Change-Id: I05f82e2af0ca822cd6cd5571ffc3845f4e6a1d91
Added opcode parser of the F.E.H.L.E.R-project for analysis of
memory access in mmu-abort handling, tracing, etc.
Change-Id: I5912fa4a4d51ee0501817c43bae05e87ac0e9b90
Added performance monitor hw-function cycle count.
Also fix for single-stepping exit, some additional register
exits and prevention of reboot failures.
Change-Id: I74196905dc39ecc14ae78366e7e1cb70ec7092f1
Polling of current target system state was done non-blocking until now.
Because of this, when the target was executing a longer time, the main-loop
was walked through several times and so unwanted state changes were
triggered. After this fix, the polling of execution state is blocking
in a while-loop until the target system hits any halting condition.
Also added some minor fixes
Change-Id: I4cbbef6eb6ff6ff8a3451affb8409a0df6a95fc5
Previously for correct termination, the PandaController called
the finish-function of the openocd wrapper, invoked a coroutine
switch and waited for the openocd wrapper to finish up and switch
coroutine again, so the PandaController could exit with correct
exitStatus. Now the openocd-wrapper directly exits with chosen
exit status.
Change-Id: I8d318a4143c53340896ccee4d059a0d79fdcfe89
In the OpenOCD config file for omap4460 an old definition of
Cortex-A9 CPUs was used. Without this fix, OpenOCD would not
start up.
Additionally this commit reduces the number of available Cortex-M
debug targets to one for the sake of simplicity.
Change-Id: Ic690bebd3d171ac0773bb0f1a8087ac96127fb6e
Normally OpenOCD reads all GP-Registers at halt, which is slow.
Restriction to only necessary Registers 1 and 15.
In the normal use case of OpenOCD this performance reduction does
not matter, because debugging does not need to be optimized for
performance. It just has to be faster than the human perception.
If we need to get the values of the registers 2 to 14, these are
fetched on demand per register.
Change-Id: I8587fbcc41c18722baebca1cec074188fe4cdebb
As the openocd-executable won't be needed, the main-function just
prints a warning, which should never be seen in fail context.
Change-Id: I8e5bbd00f152f68058f946b68201c0917db9ec9a
* If included by cpp-file, this will cause trouble. So it gets restricted
to use in c only.
* Prevent usage of "new" as variable name
* No redifinition of true and false, if included by C++
* Definition of bool fixed
Change-Id: Ic5403bd576afd9d2900a8ecfbcfdc50561ba0633
Including
* Main loop for controlling pandaboard
* Modification routines like setting halt conditions, reading
or writing Memory, Registers, etc.
* Timers
The *.hpp file is defined as *.hpp.in, because the absolute path to
config file must be set by CMake-Script (Will be introduced in later
commit)
Change-Id: I648df4916877dae550943bbb9b264b8d662689b7
After each simulator break, T32Tracer retrieves the latest (16)
trace records from the T32. Memory address and value can now
be evaluated easily from the trace record.
TODO:Nevertheless we still have to traverse the trace to
find the instruction causing the access.
The T32 can simulate bare instruction sets without periphery.
For the Cortex-M3 we have complete NVIC model including Systick Timer.
Currently a simple CiAO can run on the simulator.
TODO:
- Let memlogger log all memory accesses.
- Interact with FailT32 for a complete simulation/FI
For the T32 variant we have to evaluate the memory
access instruction to find out, which memory address
was accessed.
Dissassmbly by OpenOCDs arm_disassembler.hpp/.cc:
- fine for ARM / Thumb1
- needs fixes for Thumb2 :( (currently doing that..)
Currently working:
- Connect/Disconnect, Read CPU info
- CMM Script generation and T32 startup via cmake (make runt32)
- Read/Write Register, Read Program Pointer
- Read/Write Memory
- Single Breakpoint
- Setting Memory Breakpoint
TODO:
- Fix mock aspect for T32_GetRam.
- Fix Thumb2 bit in function addresses from ELFReader
- Evaluate memory breakpoint hit
