Commit Graph

64 Commits

Author SHA1 Message Date
eb17e9ef82 core/sal: move command-line parameter passing to SC::startup() 2013-03-14 22:29:43 +01:00
422db3e21d core/util: indirection to CommandLine class added to make bochs compile
If CommandLine.hpp and (indirectly) optionparser.h is #included in
FailBochsInit.ah, bochs compilation fails (for, e.g., gui/x.cc, at least
on Debian 6).
2013-03-14 18:13:13 +01:00
ad3c185b61 core/util: Added CommandLine interface (for bochs) 2013-03-11 15:29:26 +01:00
3cc40e62c7 A few CPUState-related methods should be const (getter)
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2084 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-14 14:45:22 +00:00
3307987895 Added missing virtual Destructor, fixes gcc warning
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2068 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-07 00:51:19 +00:00
d9808c0fca DEBUG flag in BochsController not needed anymore
It is a remnant of former times. ;-)

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2065 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-06 15:39:54 +00:00
5c4b132550 ~SimulatorController: do not free ConcreteCPU object ptr in the base class
In fact, delete should be called in the destructor of each derived class (BochsController and Gem5Controller at the moment).

Additionally, this is the reason why ~SimulatorController is declared as virtual.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2064 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-06 15:39:50 +00:00
552a5fb4ac coding-style++, comments++, FIXMEs++
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2063 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-06 15:39:46 +00:00
e98b18e678 Breakpoint aspects updated
The aspects respond to the new CONFIG_EVENT_BREAKPOINT_RANGE flag now.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2040 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-31 14:32:14 +00:00
125914a305 BochsRegister.hpp and BochsRegisterIDs.hpp not needed anymore
The includes of these headers have already been removed from the experiments. In the current code, the content of the header BochsRegister.hpp is rather simply copied to x86/Architecture.hpp. It is therefore necessary to revisit the code soon (especially the FIXME related to register IDs).

Another problem is that there is no generalization of register IDs. Thus, all experiments are currently specific to a concrete architecture (which is not desired).

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2010 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-17 13:41:23 +00:00
03b4356598 Bugfix: Let Bochs' trigger breakpoint events even in case of rep-instructions
This reverts the solution of a former commit (see git hash e1f6601d8494bcb002e89543a9334e053f0e69d3). All additional changes proposed in that commit have been deleted and the major work is now done by the aspect header BreakRepeatInstr.ah: It ensures the condition in the methods repeat() and repeat_ZF() if (BX_CPU_THIS_PTR async_event) ... to be always true which causes Bochs to leave these methods immediately. This, in turn, involves a call to defineCPULoopJointPoint(), yielding a breakpoint event in Fail.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2009 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-17 13:41:19 +00:00
edf44aec28 Bugfixes for aspect headers due to architecure-related changes.
Now, each aspect calls it's corresponding event headler by providing the new CPU object pointer as well.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2007 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-17 13:41:11 +00:00
214bb36b47 onIOPort needs to have a ConcreteCPU argument as well; detectCPU() added
detectCPU() allows us to easily retrieve the current Fail-CPU object which is a regular use case in the aspect headers, now. (Another solution would be a slice in the Bochs CPU class which inserts a reference to the Fail CPU object. Maybe we 'll implement this at a later point.)

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2006 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-17 13:41:07 +00:00
f8aa1237e9 Make FailBochs compile again (after changes in r1966).
For now, only breakpoints are working. Other event sources need to be revised, too.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1981 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:43 +00:00
d019f64bf5 Export Bochs 64 bit ability (if enabled).
This is required to add the architecture-dependent registers.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1979 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:35 +00:00
25f75b299c coding style fixed, some FIXMEs and comments added.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1974 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:17 +00:00
hsc
5135c79c05 TimerListener: microsecond granularity (ms is too coarse)
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1952 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-11-23 15:35:08 +00:00
hsc
9c3755363b bochs bugfix: store the timer ID for correct deregistration
Over a few indirections, this broke Bochs' 16550 UART simulation after
transferring a few hundreds of bytes.  The UART uses internal timers to
simulate the configured baud rate; these timers cease to work after
repeated misuse from the Fail/Bochs bridge.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1887 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-11-06 18:29:45 +00:00
hsc
1668e21ce1 bochs: removed preprocessor nonsense
It doesn't make sense to let timer (de)registration depend on
CONFIG_EVENT_BREAKPOINTS.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1886 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-11-06 18:29:41 +00:00
0b8710872b Removed BochController debug stuff. Merged: BochsController::onBreakpoint -> SimCon::onBreakpoint.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1883 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-11-06 11:40:05 +00:00
hsc
0d1618746c sal/bochs: move register IDs to a separate file
This is necessary as a temporary fix: Currently, campaign code cannot use
Fail*'s architecture abstractions at all (e.g., we cannot iterate over all
existing GP registers).  Until this is corrected by separating a concrete
backend and architecture information (the latter being usable by a
campaign), we now at least can use register IDs.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1792 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-22 15:36:09 +00:00
hsc
a911ebb353 Revert "explicit aspect activation"
Unfortunately, this does not (yet) work as advertised.  I need to fight another
round of CMake battles before retrying.  Reverting to previous state for now.

This reverts r1753.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1767 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-19 09:45:00 +00:00
hsc
a29ad39f5e explicit aspect activation
ag++ is now called with a list of currently active aspect headers
(ag++ -a aspect1.ah -a aspect2.ah ...).  This resolves several problems at
once:
 -  Build directories may be positioned arbitrarily now, they need not be
    a subdirectory of the project anymore.
 -  Multiple build directories can coexist within the project tree.  Before
    this commit, the generated instantiate-*.ah aspect headers disturbed
    neighboring build trees.
 -  Due to this, the regression test should be runnable much more easily
    now.
 -  The build time was reduced by an average of about 10%.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1753 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-17 15:22:23 +00:00
hsc
6100472e1b redundant include
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1746 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-16 16:59:46 +00:00
171d178309 SimCon interface update: save returns a boolean, now (+ redundant virtual keywords removed).
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1724 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-05 12:12:56 +00:00
42a75fa128 Documentation / corrected Bochs timer
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1718 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-05 09:41:41 +00:00
0c3d365368 bugfix: Add BochsListener to CMakeLists, workaround for onTimerTrigger
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1717 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-04 15:38:56 +00:00
2b79e83d72 Make it comile again with CONFIG_FAST_BREAKPOINTS enabled (avoid include cycle, see r1706), set timer id correctly (setId), coding-style + comment fix.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1712 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-04 11:20:31 +00:00
7d49b6f063 Simulator specific listener are now implemented using aspects instead of an additional inheritance level
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1706 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-02 11:42:18 +00:00
fd102c01ea Important bugfix: passing the instruction cache entry pointer
does not account for arrays of instructions provided
by one virtual instruction trace cache entry ->
passing the current instruction directly.
ALUInstr not yet completely tested.


git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1704 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-10-01 17:51:34 +00:00
00b16ae5d0 (Fail)Bochs bug documented in more detail: TimerListener cannot be added at boot time.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1697 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-27 09:32:32 +00:00
057c216dc0 Removed BufferCache stuff (fast breakpoints will do the job, see r1685).
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1686 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-25 11:36:19 +00:00
0cb6b39490 Aspect-based implementation of fast breakpoints added (optional).
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1685 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-25 10:10:02 +00:00
hsc
4e321409b7 several FIXMEs on virtual BaseListener functions
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1638 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-13 20:08:39 +00:00
hsc
f913d3f1ac disabling debug output
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1623 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-12 16:10:38 +00:00
hsc
f795bf63c4 qemu: IOPortListener
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1622 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-12 16:05:18 +00:00
hsc
d40113c535 qemu: MemWriteListener specialization
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1619 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-12 14:07:15 +00:00
hsc
8cadb3e5c6 bochs: version not hardcoded anymore
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1617 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-12 14:07:10 +00:00
hsc
2fed94ae49 global interrupt_to_fire seems not to be Bochs-specific at the moment
FIXME: This shouldn't be a global variable (probably a SimulatorController
member?).  Reconsider interrupt generation being part of the generic
interface.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1612 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-11 17:10:11 +00:00
hsc
4f18dd945e MemoryController: guestToHost should not be part of the abstract iface
Not all backends have their memory mapped to a Fail*-accessible address.
Especially hardware targets can only be accessed indirectly.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1611 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-11 17:10:08 +00:00
hsc
e24099d4a8 Bochs aspects: check for BUILD_BOCHS everywhere
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1610 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-11 17:10:04 +00:00
hsc
10d0344505 typos
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1609 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-11 17:10:00 +00:00
402ca4ec45 Added mechanism to specialize listener + basic BPSingleListener for gem5
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1603 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-07 00:57:05 +00:00
hsc
8ca5893b69 bugfix: config header missing in save/restore/BP aspects
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1602 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-09-06 18:14:19 +00:00
9588a30f5b Interface unification: BochsController implements onBreakpoint() instead of onInstrPtrChanged().
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1510 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-08-27 12:09:45 +00:00
hsc
a22ab1744c bugfix: Bochs reboot results in invalid CPU state
Bochs' CPU loop hook is not the right place to trigger a reboot; the EIP
increment soon thereafter leaves the CPU in an invalid state:
00194392696e[CPU0 ] prefetch: EIP [00010000] > CS.limit [0000ffff]
00194392698e[CPU0 ] prefetch: EIP [00010000] > CS.limit [0000ffff]
00194392700e[CPU0 ] prefetch: EIP [00010000] > CS.limit [0000ffff]
...

Instead, do it where the "reboot" button also does it -- synchronously in a
timer handler.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1507 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-08-27 11:30:06 +00:00
ca17c793e7 Fail* now builds with hsc-simple as experiment for gem5.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1503 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-08-22 14:20:26 +00:00
9a23dbbb42 comments and coding-style fixed.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1498 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-08-16 14:26:11 +00:00
adb2bf2787 Comments + Coding-Style fixed.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1461 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-07-30 13:34:52 +00:00
hsc
ef45841b91 MemAccess aspect: only save rmw_address if MEMREAD/MEMWRITE is enabled
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1456 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-07-16 18:21:09 +00:00