Commit Graph

189 Commits

Author SHA1 Message Date
dd81913f2c Revert "gem5: The serializeAll(path) method don't have to be invoked on the root object."
This reverts commit 60735f254e.
2013-05-22 17:38:39 +02:00
60735f254e gem5: The serializeAll(path) method don't have to be invoked on the root object.
The checkpoint which is produced by this save method is a little bit
different to the checkpoint which is produced by the --take-checkpoint
command. It differs in the save-parameters so_state, funcExeInst, intRegs,
_upc, _nupc, _when. Tests have shown that it probably does not affect the
course of the program execution.

Change-Id: I19b3fc809288224532e0ed6b7910a45115cb1c5d
2013-05-22 15:56:04 +02:00
d525005990 gem5: save/restore moved to Gem5Controller
Change-Id: I0ce72f04a8de88f4f8b6c1f0bba7a9097c82e107
2013-05-22 13:54:55 +02:00
515eb9973b Fail* CPUState: set/getRegisterContent() uses "const Register*" as 1st param
The first parameter (Register* reg) is only used as input (const-correctness).

Change-Id: I5a75a9f7378913e491a8a22872f51a385e910af6
2013-05-07 14:48:36 +02:00
924b40615d gem5: revisited register implementation
The previous implementation wasn't in a working state because
the register content retrieval was buggy. (For example, RT_FP
does *not* denote a "floating point" register. Instead, it is
the frame pointer!)

Change-Id: I31fd80d374c945adaf35b47958d6437a8e2d48c3
2013-05-07 14:45:54 +02:00
619f62b09f gem5: added getMnemonic() (requires breakpoints)
Change-Id: I5a2862a0ad3c3d506189a6196682e227205ebe09
2013-05-07 14:42:59 +02:00
699f14cf0f Merge "gem5: revisited breakpoint implementation" 2013-05-07 13:06:04 +02:00
392a6e6eb8 core/sal: correct timer ticks/sec calculation
Change-Id: I0971fe8a21c9ed3415d98b5e6387299beb3121e6
2013-04-29 14:15:36 +02:00
33c0584dda gem5: revisited breakpoint implementation
Now, the gem5 implementation equals the Bochs variant. Note that it's
*not* necessary to enable CONFIG_EVENTS_BREAKPOINTS_RANGE in order to
use range breakpoints.
In addition, gem5 distinguishes between macro- and microops. With the
new implementation, onBreakpoint() is only called when a macroop
changes.

Change-Id: Ib86d1802fc70c20d22ca1a1ece0e8d1221b2e7db
2013-04-29 13:23:58 +02:00
f364024cba Typos in BochsController.hpp fixed
Change-Id: Ib94d63707fdeb3e0dc77cccd3ffde04df25329c2
2013-04-23 14:34:27 +02:00
2910e8462e Merge "Removed OVP-related (source) files/code (backend discarded)." 2013-04-23 14:27:02 +02:00
0f16f18d75 cosmetics
Change-Id: Ifae805ae1e2dac95324e054af09a7b70f5d5b60c
2013-04-22 14:24:02 +02:00
03bcf7bfc8 Removed OVP-related (source) files/code (backend discarded).
Change-Id: Ibf8065d9fe760640e5744896b764f9ebb6d2fa69
2013-04-10 15:16:46 +02:00
e5fe9dd525 core/sal: interface for backend-specific notion of time
This adds an interface for a backend-specific notion of time, e.g. CPU
cycles since simulator start, and a concrete implementation for the
Bochs backend.  This is needed to record CPU idle times (e.g., HLT
instruction), and for target backends capable of more timing-accurate
execution.

This change also modifies the tracing plugin to add the time to all
trace events.

Change-Id: I93ac1d54c07f32b0b8f84f333417741d8e9c8288
2013-04-10 13:00:49 +02:00
08febe5819 gem5 build system improved
Encapsulated gem5-specific code into wrapper functions to separate the
build process (Fail: CMake, gem5: scons). Added some gem5-related FIXMEs.

Another CMake related FIXME added. +some cosmetics.

Change-Id: Id84b480127b1f13aed6a0ee97f3583f410d531c5
2013-04-08 17:57:06 +02:00
0654967f39 A small hint about the current trap-handler impl. in gem5
Change-Id: Ia8c80152bc0eb0f032e7ddfbfa2fd9b246e34697
2013-04-03 16:55:33 +02:00
a328a21887 Renamed x86- and ARM-specific source files (for improved readability).
Updated include paths and CMake config appropriately

Change-Id: Ida5045cde0458b3031e64b73853fe5f58ef5a9d6
2013-04-03 16:46:51 +02:00
74bd3e99e5 Merge "sal/bochs: strict-aliasing warning removed" 2013-04-03 13:14:44 +02:00
3fb58de4a5 core/sal: pass commandline parameters by reference
This allows the commandline parameter parser to modify argc, as it finds
arguments for the Fail* client.  Additionally argv is correctly null
terminated when removing arguments.

This fixes a bug introduced in eb17e9ef82.

Change-Id: Iabe84530790ecb7c587b0af139127015aad868d5
2013-04-02 21:47:39 +02:00
19e0578474 sal/bochs: strict-aliasing warning removed
This fixes a GCC warning: "warning: dereferencing type-punned pointer will
break strict-aliasing rules [-Wstrict-aliasing]"

Change-Id: I4f079b239adeb9d3c2ac2daaa2a1333d20046505
2013-04-02 14:11:45 +02:00
0eeec70570 sal/bochs: compress memory images on save/restore
This saves a lot of disk space for campaigns with many saved VM states.

Change-Id: I19c68d8545bb9b299f113d43d44202a517520b09
2013-03-28 17:12:25 +01:00
72a021be38 misc cleanup, comments, whitespace, gitignore
Change-Id: I6250339ddc5807879c98da2d204418e7b4898a73
2013-03-27 17:37:03 +01:00
ff2aec5d7e T32SIM: evaluating mem access via trace correctly :) 2013-03-21 18:58:04 +01:00
b8e706b1a5 T32SIM: Integrating Tracing feature of the T32SIM.
After each simulator break, T32Tracer retrieves the latest (16)
trace records from the T32. Memory address and value can now
be evaluated easily from the trace record.

TODO:Nevertheless we still have to traverse the trace to
find the instruction causing the access.
2013-03-21 18:57:46 +01:00
f0e26a9b63 Optionparser: Fix for non-Bochs builds. 2013-03-20 17:16:57 +01:00
739a62c60b Optionparser: FAILS for non-bochs builds!
bx_startup_flags are only present in a bochs build!
2013-03-20 16:07:02 +01:00
96ac7494e0 Moved get*Flag() methods from BochsCPU to X86CPUState class 2013-03-19 13:43:50 +01:00
794466d7d7 ~Gem5Controller() should delete it's MemoryManager object 2013-03-19 13:39:18 +01:00
f844eb0e98 Rename GenericTimerEvent -> TimerEvent 2013-03-19 13:37:18 +01:00
eb17e9ef82 core/sal: move command-line parameter passing to SC::startup() 2013-03-14 22:29:43 +01:00
422db3e21d core/util: indirection to CommandLine class added to make bochs compile
If CommandLine.hpp and (indirectly) optionparser.h is #included in
FailBochsInit.ah, bochs compilation fails (for, e.g., gui/x.cc, at least
on Debian 6).
2013-03-14 18:13:13 +01:00
ad3c185b61 core/util: Added CommandLine interface (for bochs) 2013-03-11 15:29:26 +01:00
c1f32f5a98 ElfReader: add some convenience functions 2013-03-11 15:29:25 +01:00
f586351e79 T32: Dissassembler to evaluate memory instructions.
For the T32 variant we have to evaluate the memory
access instruction to find out, which memory address
was accessed.

Dissassmbly by OpenOCDs arm_disassembler.hpp/.cc:
- fine for ARM / Thumb1
- needs fixes for Thumb2 :( (currently doing that..)
2013-03-11 12:17:53 +01:00
1fe1dbb3ed util: Added disassembler using objdump tool.
The disassembler disassembles an elf file with
an external objdump tool.
The architecture specific objdump must be configured
via cmake (ARCH_TOOL_PREFIX), e.g. arm-none-eabi- for
arm-none-eabi-objdump.
2013-03-05 21:20:25 +01:00
3501050548 T32: FailT32 support for Cortex-M3
Currently working:
 - Connect/Disconnect, Read CPU info
 - CMM Script generation and T32 startup via cmake (make runt32)
 - Read/Write Register, Read Program Pointer
 - Read/Write Memory
 - Single Breakpoint
 - Setting Memory Breakpoint

TODO:
 - Fix mock aspect for T32_GetRam.
 - Fix Thumb2 bit in function addresses from ELFReader
 - Evaluate memory breakpoint hit
2013-03-01 12:47:32 +01:00
447411da9a T32: Evalute memory map, RangeListener, MemAccess 2013-02-21 12:32:55 +01:00
205c7ec919 T32: Breakpoint test code
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2107 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-16 23:05:07 +00:00
6761268d93 T32: Added BPSingle, central T32 specific api constants
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2106 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-16 23:05:04 +00:00
2e16b8873b T32: Memory access.
Still not tested on real T32.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2105 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-16 22:05:02 +00:00
d86d18bced T32: Code cleanup.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2104 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-16 22:05:00 +00:00
39a6415001 T32: Integrated Register read/write calls
* Tested without connected Lauterbach.
  T32_* functions are mocked via aspect.

* New target t32cli, for sending T32 command cia cli. (for testing)

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2103 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-15 18:06:02 +00:00
bf9e111b9f no need for a separate fillRegisterList() method(only called once)
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2086 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-14 14:45:30 +00:00
e81517645f doc for X86CPUState added, FIXME removed
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2085 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-14 14:45:26 +00:00
3cc40e62c7 A few CPUState-related methods should be const (getter)
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2084 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-14 14:45:22 +00:00
accfba8237 coding-style++, gem5 code doc added
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2083 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-14 14:45:18 +00:00
c8a9039f36 #error msg for gem5 + x85 added (not supported yet)
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2082 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-14 14:45:13 +00:00
7f587d461c ArmArchitecture::fillRegisterList(): set textual register name appropriately
For some reasons, the compiler cannot find a matching Register::setName(const std::string&) although it is implemented in sal/Register.cc. The work around fixes this issue.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2077 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-07 14:17:49 +00:00
f96f4dd360 typo-fix
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2075 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-07 10:43:07 +00:00
3307987895 Added missing virtual Destructor, fixes gcc warning
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2068 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-07 00:51:19 +00:00