Commit Graph

9 Commits

Author SHA1 Message Date
12b539ff75 misc cleanups
This change touches several subsystems, tools and experiments
(sal, util, cmake, import-trace, generic-tracing, nanojpeg), and
changes details not worth separate commits.

Change-Id: Icd1d664d1be5cfc2212dbf77801c271183214d08
2013-09-10 17:37:25 +02:00
52723a874e sal: allow register sets to overlap
This allows a register to be a member of multiple UniformRegisterSets.
Needed to architecture-specifically store, e.g., a list of registers to
record in traces.

Change-Id: Ia5d20768540efe252a84df967d43e569f107da3a
2013-08-27 13:38:40 +02:00
552a5fb4ac coding-style++, comments++, FIXMEs++
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2063 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-06 15:39:46 +00:00
38b7064189 Make CPUArchitecure::addRegister protected: no need to modify the register config in an experiment
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2062 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-02-06 15:39:41 +00:00
582c8617d3 CPUArchitecture: iterator added to allow iterating over all registers
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2036 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-31 12:19:02 +00:00
cb429fddb2 typos fixed.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2032 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2013-01-31 12:18:47 +00:00
25f75b299c coding style fixed, some FIXMEs and comments added.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1974 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-12 13:08:17 +00:00
35753cd075 coding style++, some TODOs added.
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1967 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-05 12:27:17 +00:00
b052c0494b Architecture changes (only gem5 implementation right now):
- The register manager is gone. It's functionality is now encapsulated in the
  CPU classes.
- For the client, there is the ConcreteCPU class that encapsulates the access
  to the CPU state (including registers) and architecture details. The
  correspondig objects for the CPUs inside the simulator can be accessed
  through the SimulatorController.getCPU() function.
- Listener got a new ConcreteCPU* member to filter for which CPU the events
  should fire. The default NULL is used as wildcard for all aviable CPUs. The
  events respectively got a ConcreteCPU* member to indicate which CPU really
  fired the event.
- For the server, there is CPUArchitecture to access the architecture details.

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@1966 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
2012-12-02 17:50:46 +00:00