coding-style++, comments++, FIXMEs++
git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2063 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
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@ -64,7 +64,8 @@ public:
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*/
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*/
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UniformRegisterSet* getRegisterSetOfType(RegisterType t) const;
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UniformRegisterSet* getRegisterSetOfType(RegisterType t) const;
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protected:
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protected:
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std::vector<Register*> m_Registers;
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std::vector<Register*> m_Registers; //!< the total (!) register set
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/// a set of register subsets (each set has its own type)
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std::vector<UniformRegisterSet*> m_RegisterSubsets;
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std::vector<UniformRegisterSet*> m_RegisterSubsets;
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/**
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/**
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* Adds a new register to this set. The register object needs to be
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* Adds a new register to this set. The register object needs to be
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@ -32,8 +32,7 @@ void ArmArchitecture::fillRegisterList()
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ArmArchitecture::~ArmArchitecture()
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ArmArchitecture::~ArmArchitecture()
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{
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{
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for (std::vector<Register*>::iterator it = m_Registers.begin();
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for (std::vector<Register*>::iterator it = m_Registers.begin(); it != m_Registers.end(); it++)
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it != m_Registers.end(); it++)
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delete *it;
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delete *it;
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m_Registers.clear();
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m_Registers.clear();
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}
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}
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@ -11,15 +11,20 @@ namespace fail {
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/**
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/**
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* \class BochsCPU
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* \class BochsCPU
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* TODO.
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*
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* \c BochsCPU is the concrete CPU implementation for the Bochs x86 simulator. It
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* implements the CPU interfaces \c X86Architecture and \c X86CPUState.
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* \c X86Architecture refers to architectural information (e.g. register \a count)
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* while \c X86CPUState encapsulates the CPU state (e.g. register \a content).
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*
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*/
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*/
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class BochsCPU : public X86Architecture, public X86CPUState {
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class BochsCPU : public X86Architecture, public X86CPUState {
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private:
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private:
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unsigned int m_Id; //!< TODO: Whats this for?
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unsigned int m_Id; //!< the numeric CPU identifier (ID)
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public:
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public:
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/**
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/**
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* Initializes the Bochs CPU with the provided \c id.
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* Initializes the Bochs CPU with the provided \c id.
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* @param id TODO
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* @param id the CPU identifier (the 1st CPU is CPU0 -> id = 0, and so forth)
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*/
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*/
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BochsCPU(unsigned int id) : m_Id(id) { }
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BochsCPU(unsigned int id) : m_Id(id) { }
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/**
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/**
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@ -100,7 +105,7 @@ public:
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unsigned int getId() { return m_Id; }
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unsigned int getId() { return m_Id; }
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};
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};
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typedef BochsCPU ConcreteCPU;
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typedef BochsCPU ConcreteCPU; //!< the concrete BochsCPU type
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} // end-of-namespace: fail
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} // end-of-namespace: fail
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@ -24,14 +24,14 @@ void Gem5Controller::startup()
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bool Gem5Controller::save(const std::string &path)
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bool Gem5Controller::save(const std::string &path)
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{
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{
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connector.save(path);
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connector.save(path); // FIXME: not working?!
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return true;
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return true;
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}
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}
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void Gem5Controller::restore(const std::string &path)
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void Gem5Controller::restore(const std::string &path)
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{
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{
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connector.restore(path);
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connector.restore(path); // FIXME: not working?!
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}
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}
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// TODO: Implement reboot
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// TODO: Implement reboot
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@ -45,8 +45,7 @@ X86Architecture::X86Architecture()
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X86Architecture::~X86Architecture()
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X86Architecture::~X86Architecture()
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{
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{
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for (std::vector<Register*>::iterator it = m_Registers.begin();
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for (std::vector<Register*>::iterator it = m_Registers.begin(); it != m_Registers.end(); it++)
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it != m_Registers.end(); it++)
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delete *it;
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delete *it;
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m_Registers.clear();
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m_Registers.clear();
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}
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}
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