coding-style++, comments++, FIXMEs++

git-svn-id: https://www4.informatik.uni-erlangen.de/i4svn/danceos/trunk/devel/fail@2063 8c4709b5-6ec9-48aa-a5cd-a96041d1645a
This commit is contained in:
adrian
2013-02-06 15:39:46 +00:00
parent 38b7064189
commit 552a5fb4ac
5 changed files with 15 additions and 11 deletions

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@ -64,7 +64,8 @@ public:
*/ */
UniformRegisterSet* getRegisterSetOfType(RegisterType t) const; UniformRegisterSet* getRegisterSetOfType(RegisterType t) const;
protected: protected:
std::vector<Register*> m_Registers; std::vector<Register*> m_Registers; //!< the total (!) register set
/// a set of register subsets (each set has its own type)
std::vector<UniformRegisterSet*> m_RegisterSubsets; std::vector<UniformRegisterSet*> m_RegisterSubsets;
/** /**
* Adds a new register to this set. The register object needs to be * Adds a new register to this set. The register object needs to be

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@ -32,8 +32,7 @@ void ArmArchitecture::fillRegisterList()
ArmArchitecture::~ArmArchitecture() ArmArchitecture::~ArmArchitecture()
{ {
for (std::vector<Register*>::iterator it = m_Registers.begin(); for (std::vector<Register*>::iterator it = m_Registers.begin(); it != m_Registers.end(); it++)
it != m_Registers.end(); it++)
delete *it; delete *it;
m_Registers.clear(); m_Registers.clear();
} }

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@ -11,15 +11,20 @@ namespace fail {
/** /**
* \class BochsCPU * \class BochsCPU
* TODO. *
* \c BochsCPU is the concrete CPU implementation for the Bochs x86 simulator. It
* implements the CPU interfaces \c X86Architecture and \c X86CPUState.
* \c X86Architecture refers to architectural information (e.g. register \a count)
* while \c X86CPUState encapsulates the CPU state (e.g. register \a content).
*
*/ */
class BochsCPU : public X86Architecture, public X86CPUState { class BochsCPU : public X86Architecture, public X86CPUState {
private: private:
unsigned int m_Id; //!< TODO: Whats this for? unsigned int m_Id; //!< the numeric CPU identifier (ID)
public: public:
/** /**
* Initializes the Bochs CPU with the provided \c id. * Initializes the Bochs CPU with the provided \c id.
* @param id TODO * @param id the CPU identifier (the 1st CPU is CPU0 -> id = 0, and so forth)
*/ */
BochsCPU(unsigned int id) : m_Id(id) { } BochsCPU(unsigned int id) : m_Id(id) { }
/** /**
@ -100,7 +105,7 @@ public:
unsigned int getId() { return m_Id; } unsigned int getId() { return m_Id; }
}; };
typedef BochsCPU ConcreteCPU; typedef BochsCPU ConcreteCPU; //!< the concrete BochsCPU type
} // end-of-namespace: fail } // end-of-namespace: fail

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@ -24,14 +24,14 @@ void Gem5Controller::startup()
bool Gem5Controller::save(const std::string &path) bool Gem5Controller::save(const std::string &path)
{ {
connector.save(path); connector.save(path); // FIXME: not working?!
return true; return true;
} }
void Gem5Controller::restore(const std::string &path) void Gem5Controller::restore(const std::string &path)
{ {
connector.restore(path); connector.restore(path); // FIXME: not working?!
} }
// TODO: Implement reboot // TODO: Implement reboot

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@ -45,8 +45,7 @@ X86Architecture::X86Architecture()
X86Architecture::~X86Architecture() X86Architecture::~X86Architecture()
{ {
for (std::vector<Register*>::iterator it = m_Registers.begin(); for (std::vector<Register*>::iterator it = m_Registers.begin(); it != m_Registers.end(); it++)
it != m_Registers.end(); it++)
delete *it; delete *it;
m_Registers.clear(); m_Registers.clear();
} }