diff --git a/src/core/sal/CPU.hpp b/src/core/sal/CPU.hpp
index 5490baa6..27a14135 100644
--- a/src/core/sal/CPU.hpp
+++ b/src/core/sal/CPU.hpp
@@ -64,7 +64,8 @@ public:
 	 */
 	UniformRegisterSet* getRegisterSetOfType(RegisterType t) const;
 protected:
-	std::vector<Register*> m_Registers;
+	std::vector<Register*> m_Registers; //!< the total (!) register set
+	/// a set of register subsets (each set has its own type)
 	std::vector<UniformRegisterSet*> m_RegisterSubsets;
 	/**
 	 * Adds a new register to this set. The register object needs to be
diff --git a/src/core/sal/arm/Architecture.cc b/src/core/sal/arm/Architecture.cc
index 9b1b2df3..17052e8e 100644
--- a/src/core/sal/arm/Architecture.cc
+++ b/src/core/sal/arm/Architecture.cc
@@ -32,8 +32,7 @@ void ArmArchitecture::fillRegisterList()
 
 ArmArchitecture::~ArmArchitecture()
 {
-	for (std::vector<Register*>::iterator it = m_Registers.begin();
-		 it != m_Registers.end(); it++)
+	for (std::vector<Register*>::iterator it = m_Registers.begin(); it != m_Registers.end(); it++)
 		delete *it;
 	m_Registers.clear();
 }
diff --git a/src/core/sal/bochs/BochsCPU.hpp b/src/core/sal/bochs/BochsCPU.hpp
index 277803b7..0407acab 100644
--- a/src/core/sal/bochs/BochsCPU.hpp
+++ b/src/core/sal/bochs/BochsCPU.hpp
@@ -11,15 +11,20 @@ namespace fail {
 
 /**
  * \class BochsCPU
- * TODO.
+ * 
+ * \c BochsCPU is the concrete CPU implementation for the Bochs x86 simulator. It
+ * implements the CPU interfaces \c X86Architecture and \c X86CPUState.
+ * \c X86Architecture refers to architectural information (e.g. register \a count)
+ * while \c X86CPUState encapsulates the CPU state (e.g. register \a content).
+ * 
  */
 class BochsCPU : public X86Architecture, public X86CPUState {
 private:
-	unsigned int m_Id; //!< TODO: Whats this for?
+	unsigned int m_Id; //!< the numeric CPU identifier (ID)
 public:
 	/**
 	 * Initializes the Bochs CPU with the provided \c id.
-	 * @param id TODO
+	 * @param id the CPU identifier (the 1st CPU is CPU0 -> id = 0, and so forth)
 	 */
 	BochsCPU(unsigned int id) : m_Id(id) { }
 	/**
@@ -100,7 +105,7 @@ public:
 	unsigned int getId() { return m_Id; }
 };
 
-typedef BochsCPU ConcreteCPU;
+typedef BochsCPU ConcreteCPU; //!< the concrete BochsCPU type
 
 } // end-of-namespace: fail
 
diff --git a/src/core/sal/gem5/Gem5Controller.cc b/src/core/sal/gem5/Gem5Controller.cc
index b05f6aad..439e3f27 100644
--- a/src/core/sal/gem5/Gem5Controller.cc
+++ b/src/core/sal/gem5/Gem5Controller.cc
@@ -24,14 +24,14 @@ void Gem5Controller::startup()
 
 bool Gem5Controller::save(const std::string &path)
 {
-	connector.save(path);
+	connector.save(path); // FIXME: not working?!
 
 	return true;
 }
 
 void Gem5Controller::restore(const std::string &path)
 {
-	connector.restore(path);
+	connector.restore(path); // FIXME: not working?!
 }
 
 // TODO: Implement reboot
diff --git a/src/core/sal/x86/Architecture.cc b/src/core/sal/x86/Architecture.cc
index 07cc7e04..4a121f77 100644
--- a/src/core/sal/x86/Architecture.cc
+++ b/src/core/sal/x86/Architecture.cc
@@ -45,8 +45,7 @@ X86Architecture::X86Architecture()
 
 X86Architecture::~X86Architecture()
 {
-	for (std::vector<Register*>::iterator it = m_Registers.begin();
-		 it != m_Registers.end(); it++)
+	for (std::vector<Register*>::iterator it = m_Registers.begin(); it != m_Registers.end(); it++)
 		delete *it;
 	m_Registers.clear();
 }