Commit Graph
17 Commits
Author SHA1 Message Date
Huang QiandGitHub 0af7522e3e Fix fail to get builtin functions in indirect call (XIP) mode (#829)
Fix fail to get builtin functions in indirect call (XIP) mode, e.g.
function aot_alloc_frame, aot_memory_init, aot_table_init and so on.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-11-11 14:14:21 +08:00
Huang QiandGitHub 3fa91df754 Simplify some string size calculation when emitting AOT file (#813)
Simplify some string size calculation when emitting AOT file

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-11-01 20:03:13 +08:00
Huang QiandGitHub 51a00a4c2b Disable source debugging by default (#804)
For cmake based project, there are default values in .cmake,
but for other build system, may these symbols were not defined in their
build system and warnings (XXX is not defined) were generated while building.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-10-26 18:52:30 +08:00
Huang QiandGitHub a121e45a1e Simplify build setup for zephyr (#789)
Zephyr can apply board specific .conf and .overlay automatically,
move .conf to boards to make it easy to support different board without
addition command parameters.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-10-15 20:15:17 +08:00
Huang Qi b31804b64e Apply aot intrinsics to riscv
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Change-Id: If1e813f5f8ead2c0d9b640f8ea4e87e2155db534
2021-09-09 07:59:12 +00:00
Huang QiandGitHub 3953f819bc Use builtin intrinsic for float/integer conversion (#719) 2021-09-02 18:19:19 +08:00
Huang QiandGitHub cef7d35be1 Implement float and integer conversion intrinsics (#718) 2021-09-02 16:39:53 +08:00
Huang QiandGitHub bb0e4503cb Move type definition of IntCond and FloatCond to aot.h (#713) 2021-09-02 12:49:01 +08:00
Huang QiandGitHub 1687b7be32 Add missing symbols from libgcc for thumb platform (#712)
Add missing aot relocation symbols from libgcc for thumb platform

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-09-01 18:26:03 +08:00
Huang QiandGitHub 5d2882f05f Make aot intrinsic flags readable (#711)
Make aot intrinsic flags easier to read and understand

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-09-01 18:24:16 +08:00
Huang QiandGitHub 6ef74778c7 Correct confusing usage of intirnsic check (#707) 2021-08-27 19:03:18 +08:00
Huang QiandGitHub 6a7fd3e688 Make sp 8 byte aligned in invokeNative on ARM (#697)
Make sp 8 byte aligned in invokeNative assembly on ARM.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-08-18 10:21:38 +08:00
Huang QiandGitHub 8fd89bd415 Implement clock() wrapper for built-in libc (#691) 2021-08-07 21:21:25 +08:00
Huang QiandGitHub 62fb3c9a89 Unify product-mini main.c implementation for POSIX compatible system (#675)
Unify product-mini main.c implementation for POSIX compatible system: create a shared main.c under platforms/posix/main.c, and in other POSIX platforms' main.c, just keep a line "#include ../posix/main.c".

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-07-29 14:38:25 +08:00
Huang QiandGitHub 586752735b Enable to build wamrc with custom llvm and fix some compile warnings (#672)
Enable to build wamrc with custom llvm, enable to auto detect processor on apple silicon, and fix some compile warnings.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-07-26 09:29:19 +08:00
Huang QiandGitHub 04e7afe55d Update documents (#669)
Update CI rules to improve CI build speed, update document about arch support and update document of wamrc help.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
2021-07-22 13:52:48 +08:00
e4023c8e02 Implement AOT support for RISCV (#649)
Enable RISCV AOT support, the supported ABIs are LP64 and LP64D for riscv64, ILP32 and ILP32D for riscv32.
For wamrc:
    use --target=riscv64/riscv32 to specify the target arch of output AOT file,
    use --target-abi=lp64d/lp64/ilp32d/ilp32 to specify the target ABI,
    if --target-abi isn't specified, by default lp64d is used for riscv64, and ilp32d is used for riscv32.

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Co-authored-by: wenyongh <wenyong.huang@intel.com>
2021-07-22 11:16:47 +08:00