Fix Zifencei extension issue in RISC-V (#2807)

Refer to: https://github.com/bytecodealliance/wasm-micro-runtime/pull/2805
2023-11-23 10:23:33 +08:00
parent 2175910bac
commit cb44e56b4e
1 changed files with 4 additions and 0 deletions
--- a/core/iwasm/aot/arch/aot_reloc_riscv.c
+++ b/core/iwasm/aot/arch/aot_reloc_riscv.c
@ -177,7 +177,11 @@ rv_set_val(uint16 *addr, uint32 val)
    *addr = (val & 0xffff);
    *(addr + 1) = (val >> 16);

+#ifdef __riscv_zifencei
    __asm__ volatile("fence.i");
+#else
+    __asm__ volatile("fence");
+#endif
 }

 /* Add a val to given address */