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systemverilog-rom-assembler/programs/nop_and_jump.sv
2023-03-30 16:34:19 +02:00

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Systemverilog

`default_nettype none
module ROM(
input var logic[7:0] address,
output var logic[7:0] dataout
);
always @(address) case (address)
8'b00000001: dataout = 8'b11000000;
8'b00000010: dataout = 8'b00000000;
8'b00000011: dataout = 8'b11000100;
default: dataout = 8'b00000000;
endcase
endmodule