35 lines
1.0 KiB
Systemverilog
35 lines
1.0 KiB
Systemverilog
`default_nettype none
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module ROM(
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input var logic[7:0] address,
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output var logic[7:0] dataout
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);
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always @(address) case (address)
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8'b00000001: dataout = 8'b00110000;
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8'b00000010: dataout = 8'b10000110;
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8'b00000011: dataout = 8'b00110001;
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8'b00000100: dataout = 8'b10000110;
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8'b00000101: dataout = 8'b00110010;
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8'b00000110: dataout = 8'b10000110;
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8'b00000111: dataout = 8'b00110011;
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8'b00001000: dataout = 8'b10000110;
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8'b00001001: dataout = 8'b00110100;
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8'b00001010: dataout = 8'b10000110;
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8'b00001011: dataout = 8'b00110101;
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8'b00001100: dataout = 8'b10000110;
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8'b00001101: dataout = 8'b00110110;
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8'b00001110: dataout = 8'b10000110;
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8'b00001111: dataout = 8'b00110111;
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8'b00010000: dataout = 8'b10000110;
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8'b00010001: dataout = 8'b00111000;
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8'b00010010: dataout = 8'b10000110;
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8'b00010011: dataout = 8'b00111001;
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8'b00010100: dataout = 8'b10000110;
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8'b00010101: dataout = 8'b00000000;
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8'b00010110: dataout = 8'b11000100;
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default: dataout = 8'b00000000;
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endcase
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endmodule
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