31 lines
2.0 KiB
Markdown
31 lines
2.0 KiB
Markdown
# README
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Small assembler that generates SystemVerilog ROM modules for [this](https://gitlab.com/ChUrl/quartus-8-bit-cpu).
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## Usage
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`svrasm -i <inputfile> -o <outputfile>`
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## Instructionset
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| Instruction | 1. Operand | 2. Operand | Note |
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|-------------|-----------------------------|-----------------|----------------------------------------|
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| MOV | Constant or Source Register | Target Register | |
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| AND | NONE | NONE | Works on reg1 and reg2, result in reg3 |
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| OR | NONE | NONE | Works on reg1 and reg2, result in reg3 |
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| NAND | NONE | NONE | Works on reg1 and reg2, result in reg3 |
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| NOR | NONE | NONE | Works on reg1 and reg2, result in reg3 |
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| ADD | NONE | NONE | Works on reg1 and reg2, result in reg3 |
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| SUB | NONE | NONE | Works on reg1 and reg2, result in reg3 |
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| JMP | NONE | NONE | Works on reg3 |
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| JEQ | NONE | NONE | Works on reg3 |
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| JLE | NONE | NONE | Works on reg3 |
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| JLEQ | NONE | NONE | Works on reg3 |
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| NOP | NONE | NONE | Works on reg3 |
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| JNEQ | NONE | NONE | Works on reg3 |
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| JGR | NONE | NONE | Works on reg3 |
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| JGEQ | NONE | NONE | Works on reg3 |
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Line comments are recognized, indicated by `#`.
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