christoph/systemverilog-rom-assembler
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Reassemble example programs

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Christoph Urlacher
2023-03-29 19:14:00 +02:00
parent a7f4bf6e92
commit f554efcd7d
12 changed files with 89 additions and 68 deletions
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programs/nop_and_jump.sv Normal file
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`default_nettype none
module ROM(
input var logic[7:0] address,
output var logic[7:0] dataout
);
always @(address) case (address)
case 8'b00000000: dataout = 8'b11000000;
case 8'b00000001: dataout = 8'b00000000;
case 8'b00000010: dataout = 8'b11000100;
default: dataout = 8'b00000000;
endcase
endmodule