christoph/systemverilog-rom-assembler
1
Fork 0
Code Activity

Fix an output format bug

Browse Source
This commit is contained in:
Christoph Urlacher
2023-03-29 19:24:21 +02:00
parent f554efcd7d
commit 95d911c3be
1 changed files with 2 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/main.cpp
View File

@ -68,24 +68,20 @@ auto write(const std::string &output_file, const std::vector<std::string> &outpu
return false; return false;
} }
// TODO: Output the assembly in a comment next to the case entry
ofs << "`default_nettype none\n\n" ofs << "`default_nettype none\n\n"
<< "module ROM(\n" << "module ROM(\n"
<< " input var logic[7:0] address,\n" << " input var logic[7:0] address,\n"
<< " output var logic[7:0] dataout\n" << " output var logic[7:0] dataout\n"
<< ");\n\n" << ");\n\n"
<< " always @(address) case (address)\n"; << " always @(address) case (address)\n";
for (uint32_t i = 0; i <= 255; ++i) { for (uint32_t i = 0; i <= 255; ++i) {
if (i < output_string.size()) { if (i < output_string.size()) {
ofs << " case 8'b" << std::bitset<8>(i).to_string() << ": dataout = 8'b" << output_string[i] << ";\n"; ofs << " 8'b" << std::bitset<8>(i).to_string() << ": dataout = 8'b" << output_string[i] << ";\n";
} }
} }
ofs << " default: dataout = 8'b00000000;\n" ofs << " default: dataout = 8'b00000000;\n"
<< " endcase\n\n" << " endcase\n\n"
<< "endmodule" << std::endl; << "endmodule" << std::endl;
ofs.flush(); ofs.flush();