110 lines
2.4 KiB
Systemverilog
110 lines
2.4 KiB
Systemverilog
`default_nettype none
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module CPU(
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input var logic enable,
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input var logic clock,
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input var logic reset
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);
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// Decoder
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var logic fetch, decode, execute, writeback;
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var logic clk;
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assign clk = enable && clock; // Only clock the CPU when enabled
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Decoder dec(
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.clock(clk),
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.reset(reset),
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.fetch(fetch),
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.decode(decode),
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.execute(execute),
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.writeback(writeback)
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);
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// Program Counter
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var logic pc_set;
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var logic[7:0] pc_in;
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var logic[7:0] pc_out;
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Counter pc(
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.clock(fetch), // WARNING: Phase 1 - Fetch
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.reset(reset),
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.decrement(0),
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.setvalue(pc_set),
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.valuein(pc_in),
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.valueout(pc_out)
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);
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// ROM (Instruction Memory)
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var logic[7:0] rom_data;
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ROM rom(
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.address(pc_out),
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.dataout(rom_data)
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);
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// Controller
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var logic[1:0] ctrl_opcode;
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var logic ctrl_regsset, ctrl_pcset;
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var logic[2:0] ctrl_regssavesel, ctrl_regsloadsel, ctrl_aluopc, ctrl_condopc;
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Controller ctrl(
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.clock(decode), // WARNING: Phase 2 - Decode
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.reset(reset),
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.databus(rom_data),
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.opcode(ctrl_opcode),
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.regs_set(ctrl_regsset),
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.regs_savesel(ctrl_regssavesel),
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.regs_loadsel(ctrl_regsloadsel),
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.alu_opc(ctrl_aluopc),
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.cond_opc(ctrl_condopc),
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.pc_set(ctrl_pcset)
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);
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// Register Bank
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var logic[7:0] regs_savebus;
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var logic[7:0] regs_loadbus;
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var logic[7:0] regs_jumptarget;
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var logic[7:0] regs_aluopA;
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var logic[7:0] regs_aluopB;
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var logic[7:0] regs_aluresult;
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RegisterFile regs(
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.clock(writeback), // WARNING: Phase 4 - Writeback
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.reset(reset),
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.save(ctrl_regsset),
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.saveselector(ctrl_regssavesel),
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.savebus(regs_savebus),
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.loadselector(ctrl_regsloadsel),
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.loadbus(regs_loadbus),
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.jumptarget(regs_jumptarget),
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.aluoperandA(regs_aluopA),
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.aluoperandB(regs_aluopB),
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.aluresult(regs_aluresult)
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);
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// Arithmetic and Logical Unit
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var logic[7:0] alu_result;
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ALU alu(
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.clock(execute), // WARNING: Phase 3 - Execute
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.opcode(ctrl_aluopc),
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.operandA(regs_aluopA),
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.operandB(regs_aluopB),
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.result(alu_result)
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);
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// Conditional Unit
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var logic cond_result;
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ConditionalUnit cond(
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.clock(execute), // WARNING: Phase 3 - Execute
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.opcode(ctrl_condopc),
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.operand(regs_aluresult),
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.result(cond_result)
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);
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// CPU Inter-Component Connections
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assign pc_set = cond_result && ctrl_pcset;
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assign pc_in = regs_jumptarget;
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always @(execute) case (ctrl_opcode)
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2'b01: regs_savebus = alu_result;
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2'b11: regs_savebus = regs_loadbus;
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default: regs_savebus = 8'b00000000;
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endcase
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endmodule
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