christoph/quartus-8-bit-cpu
1
Fork 0
Code Activity

Add Quartus project files

Browse Source
This commit is contained in:
Christoph Urlacher
2023-03-27 23:30:38 +02:00
parent 6c9a027209
commit f21d4676c4
4 changed files with 142 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

23
CPU_nativelink_simulation.rpt Normal file
View File

@ -0,0 +1,23 @@
Info: Start Nativelink Simulation process
Info: NativeLink has detected Verilog design -- Verilog simulation models will be used
========= EDA Simulation Settings =====================
Sim Mode : RTL
Family : cyclonev
Quartus root : /nix/store/l9gl96q63whg0j0nknh5mspr9gxqprf4-quartus-prime-lite-unwrapped-20.1.1.720/quartus/linux64/
Quartus sim root : /nix/store/l9gl96q63whg0j0nknh5mspr9gxqprf4-quartus-prime-lite-unwrapped-20.1.1.720/quartus/eda/sim_lib
Simulation Tool : modelsim-altera
Simulation Language : verilog
Simulation Mode : GUI
Sim Output File :
Sim SDF file :
Sim dir : simulation/modelsim
=======================================================
Info: Starting NativeLink simulation with ModelSim-Altera software
Sourced NativeLink script /nix/store/l9gl96q63whg0j0nknh5mspr9gxqprf4-quartus-prime-lite-unwrapped-20.1.1.720/quartus/common/tcl/internal/nativelink/modelsim.tcl
Warning: File CPU_run_msim_rtl_verilog.do already exists - backing up current file as CPU_run_msim_rtl_verilog.do.bak10
Info: Spawning ModelSim-Altera Simulation software
Info: NativeLink simulation flow was successful