From f21d4676c4688273035f178f04fb5a34decdf9b8 Mon Sep 17 00:00:00 2001 From: ChUrl Date: Mon, 27 Mar 2023 23:30:38 +0200 Subject: [PATCH] Add Quartus project files --- CPU.qsf | 88 ++++++++++++++++++++++++++++++++++ CPU.qws | Bin 0 -> 3011 bytes CPU_nativelink_simulation.rpt | 23 +++++++++ Quartus_CPU.qpf | 31 ++++++++++++ 4 files changed, 142 insertions(+) create mode 100644 CPU.qsf create mode 100644 CPU.qws create mode 100644 CPU_nativelink_simulation.rpt create mode 100644 Quartus_CPU.qpf diff --git a/CPU.qsf b/CPU.qsf new file mode 100644 index 0000000..c295d6b --- /dev/null +++ b/CPU.qsf @@ -0,0 +1,88 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2020 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and any partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details, at +# https://fpgasoftware.intel.com/eula. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition +# Date created = 11:27:08 März 23, 2023 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# CPU_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone V" +set_global_assignment -name DEVICE 5CGXFC5C6F27C7 +set_global_assignment -name TOP_LEVEL_ENTITY LogicalUnit_TestBench +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:27:08 MäRZ 23, 2023" +set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)" +set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan +set_global_assignment -name SYSTEMVERILOG_FILE RegisterFile.sv +set_global_assignment -name SYSTEMVERILOG_FILE LogicalUnit.sv +set_global_assignment -name SYSTEMVERILOG_FILE InputOutput.sv +set_global_assignment -name SYSTEMVERILOG_FILE Counter.sv +set_global_assignment -name SYSTEMVERILOG_FILE ConditionalUnit.sv +set_global_assignment -name SYSTEMVERILOG_FILE ArithmeticUnit.sv +set_global_assignment -name SYSTEMVERILOG_FILE ALU.sv +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005 +set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name SYSTEMVERILOG_FILE ALU_TestBench.sv +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation +set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH LogicalUnit_TestBench -section_id eda_simulation +set_global_assignment -name EDA_TEST_BENCH_NAME ALU_TestBench -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id ALU_TestBench +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME ALU_TestBench -section_id ALU_TestBench +set_global_assignment -name FLOW_ENABLE_RTL_VIEWER ON +set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 10000 +set_global_assignment -name BOARD "Cyclone V GX Starter Kit" +set_global_assignment -name SYSTEMVERILOG_FILE LogicalUnit_TestBench.sv +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name EDA_TEST_BENCH_FILE ALU_TestBench.sv -section_id ALU_TestBench +set_global_assignment -name EDA_TEST_BENCH_NAME LogicalUnit_TestBench -section_id eda_simulation +set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id LogicalUnit_TestBench +set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME LogicalUnit_TestBench -section_id LogicalUnit_TestBench +set_global_assignment -name EDA_TEST_BENCH_FILE LogicalUnit_TestBench.sv -section_id LogicalUnit_TestBench +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/CPU.qws b/CPU.qws new file mode 100644 index 0000000000000000000000000000000000000000..ba8e725c0b2f79b23c2997f9ab0f06b6259db14d GIT binary patch literal 3011 zcmeH}!A=xG5QhI*R^ow!Cr=za7_u=LGU%%7O-b;?$-tT5&bV$?*>zcw#1J@}7@q=; z`Ubp!7q6ap5J3F?W`>vvtbuGIG24@xnyRj@uI~BM{Xea#Xw!P5Rjq5F6@5@weRZ&U z_?pTHsv=W*rbR7lmYxmlJGs50C1N~w9=*nh*Jm-)jOePRHr`d{Sf;;CWRWAepnq7- z8_d0^k7Rs6&ilMGbf!4iO(lHQ^-v8Y))S?{AM24`@g#aow55(TG^efd+9Dj$CtfFr zj{TAfGl;jOUTv>fFIN)=>=$}(mdusid5j~=l8HLN9cmmPS?tbK>-gl3($TYApW zjB*{)ROh^)P#Objdci)n*y$_G;&`7KD9=UkiVkcs~n>y2YC1i*9kQ_ zDpc7%Ma>2FsLz$5=ieAHe;kR|4l&gkkn&ZU+?6IibKaEf96_T-%%yL{b5S(8N6`zE zIKHj)Pj9Q@oCzpeFDy>RUl!Zpnm3A4_=